A processor core synthesis system in IP-based SoC design

Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    This paper proposes a new design methodology for SoCs reusing hardware IPs. In our approach, after system-level HW/SW partitioning, we use IPs for hardware parts, but synthesize a new processor core instead of reusing a processor core IP. System performs efficient parallel execution of hardware and software by taking account of a response time of hardware IP obtained by the proposed calculation algorithm. We can use optimal hardware IPs selected by the proposed hardware IPs selection algorithm. The experimental results show effectiveness of our new design methodology.

    Original languageEnglish
    Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
    Pages286-291
    Number of pages6
    Volume1
    Publication statusPublished - 2005
    Event2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai
    Duration: 2005 Jan 182005 Jan 21

    Other

    Other2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
    CityShanghai
    Period05/1/1805/1/21

    Fingerprint

    Hardware
    System-on-chip

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Science Applications
    • Computer Graphics and Computer-Aided Design

    Cite this

    Tomono, N., Kohara, S., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2005). A processor core synthesis system in IP-based SoC design. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (Vol. 1, pp. 286-291). [1466175]

    A processor core synthesis system in IP-based SoC design. / Tomono, Naoki; Kohara, Shunitsu; Uchida, Jumpei; Miyaoka, Yuichiro; Togawa, Nozomu; Yanagisawa, Masao; Ohtsuki, Tatsuo.

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 1 2005. p. 286-291 1466175.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Tomono, N, Kohara, S, Uchida, J, Miyaoka, Y, Togawa, N, Yanagisawa, M & Ohtsuki, T 2005, A processor core synthesis system in IP-based SoC design. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. vol. 1, 1466175, pp. 286-291, 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005, Shanghai, 05/1/18.
    Tomono N, Kohara S, Uchida J, Miyaoka Y, Togawa N, Yanagisawa M et al. A processor core synthesis system in IP-based SoC design. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 1. 2005. p. 286-291. 1466175
    Tomono, Naoki ; Kohara, Shunitsu ; Uchida, Jumpei ; Miyaoka, Yuichiro ; Togawa, Nozomu ; Yanagisawa, Masao ; Ohtsuki, Tatsuo. / A processor core synthesis system in IP-based SoC design. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 1 2005. pp. 286-291
    @inproceedings{61d3be6fd78f422fae64aae0478e018d,
    title = "A processor core synthesis system in IP-based SoC design",
    abstract = "This paper proposes a new design methodology for SoCs reusing hardware IPs. In our approach, after system-level HW/SW partitioning, we use IPs for hardware parts, but synthesize a new processor core instead of reusing a processor core IP. System performs efficient parallel execution of hardware and software by taking account of a response time of hardware IP obtained by the proposed calculation algorithm. We can use optimal hardware IPs selected by the proposed hardware IPs selection algorithm. The experimental results show effectiveness of our new design methodology.",
    author = "Naoki Tomono and Shunitsu Kohara and Jumpei Uchida and Yuichiro Miyaoka and Nozomu Togawa and Masao Yanagisawa and Tatsuo Ohtsuki",
    year = "2005",
    language = "English",
    isbn = "0780387368",
    volume = "1",
    pages = "286--291",
    booktitle = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

    }

    TY - GEN

    T1 - A processor core synthesis system in IP-based SoC design

    AU - Tomono, Naoki

    AU - Kohara, Shunitsu

    AU - Uchida, Jumpei

    AU - Miyaoka, Yuichiro

    AU - Togawa, Nozomu

    AU - Yanagisawa, Masao

    AU - Ohtsuki, Tatsuo

    PY - 2005

    Y1 - 2005

    N2 - This paper proposes a new design methodology for SoCs reusing hardware IPs. In our approach, after system-level HW/SW partitioning, we use IPs for hardware parts, but synthesize a new processor core instead of reusing a processor core IP. System performs efficient parallel execution of hardware and software by taking account of a response time of hardware IP obtained by the proposed calculation algorithm. We can use optimal hardware IPs selected by the proposed hardware IPs selection algorithm. The experimental results show effectiveness of our new design methodology.

    AB - This paper proposes a new design methodology for SoCs reusing hardware IPs. In our approach, after system-level HW/SW partitioning, we use IPs for hardware parts, but synthesize a new processor core instead of reusing a processor core IP. System performs efficient parallel execution of hardware and software by taking account of a response time of hardware IP obtained by the proposed calculation algorithm. We can use optimal hardware IPs selected by the proposed hardware IPs selection algorithm. The experimental results show effectiveness of our new design methodology.

    UR - http://www.scopus.com/inward/record.url?scp=84861429014&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=84861429014&partnerID=8YFLogxK

    M3 - Conference contribution

    AN - SCOPUS:84861429014

    SN - 0780387368

    SN - 9780780387362

    VL - 1

    SP - 286

    EP - 291

    BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

    ER -