A Pulse-Coupled Neural Network Simulator Using a Programmable Gate Array Technique

Kousuke Katayama, Atsushi Iwata

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

In this paper, we propose a novel pulse-coupled neural network (PCNN) simulator using a programmable gate array (PGA) technique. The simulator is composed of modified phase-locked loops (PLLs) and a programmable gate array (PGA). The PLL, which is modified by the addition of multiple inputs and multiple feedbacks, works as a neuron. The PGA, which controls the network connection, works as nodes of dendritic trees. This simulator, which has 16 neurons and 32 × 32 network connections, is designed on a chip (4.73mm × 4.73mm), and its basic operations such as synchronization, an oscillatory associative memory, and FM interactions are confirmed using circuit simulator SPICE.

Original languageEnglish
Pages (from-to)872-881
Number of pages10
JournalIEICE Transactions on Information and Systems
VolumeE86-D
Issue number5
Publication statusPublished - 2003 May
Externally publishedYes

Keywords

  • Dendritic tree
  • Phase-locked loops
  • Programmable gate array
  • Pulse-coupled neural Network
  • Reconfigurable network

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

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