TY - GEN
T1 - A Radix-4 Partial Product Generation-Based Approximate Multiplier for High-speed and Low-power Digital Signal Processing
AU - Sun, Xiaoting
AU - Guo, Yi
AU - Liu, Zhenhao
AU - Kimura, Shinji
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2019/1/17
Y1 - 2019/1/17
N2 - Power and energy minimization has become a significant design requirement for many electronic systems nowadays. As a commonly used arithmetic unit, approximate multiplier is a desirable target for high-speed and low-power digital signal processing. This paper proposes a novel design based on radix-4 partial product generation method, which reduces the height of partial product to half. A new 4-2 compressor is also proposed under the consideration of hardware and accuracy performance for partial product accumulation. As a result, the proposed design for 8-bit multiplication achieves a reduction of power, area and delay up to 49.4%, 53.4% and 48.2% compared to the conventional accurate multiplier. Meanwhile, the accuracy and hardware performance of the proposed design are also compared with several previous works and shows its effectiveness. In addition, the proposed multiplier is also applied to image processing applications without compromising the overall image quality while the power consumption is dramatically reduced.
AB - Power and energy minimization has become a significant design requirement for many electronic systems nowadays. As a commonly used arithmetic unit, approximate multiplier is a desirable target for high-speed and low-power digital signal processing. This paper proposes a novel design based on radix-4 partial product generation method, which reduces the height of partial product to half. A new 4-2 compressor is also proposed under the consideration of hardware and accuracy performance for partial product accumulation. As a result, the proposed design for 8-bit multiplication achieves a reduction of power, area and delay up to 49.4%, 53.4% and 48.2% compared to the conventional accurate multiplier. Meanwhile, the accuracy and hardware performance of the proposed design are also compared with several previous works and shows its effectiveness. In addition, the proposed multiplier is also applied to image processing applications without compromising the overall image quality while the power consumption is dramatically reduced.
KW - Digital signal processing
KW - approximate computing
KW - energy efficiency
KW - error analysis
KW - high speed
UR - http://www.scopus.com/inward/record.url?scp=85062286927&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85062286927&partnerID=8YFLogxK
U2 - 10.1109/ICECS.2018.8617854
DO - 10.1109/ICECS.2018.8617854
M3 - Conference contribution
AN - SCOPUS:85062286927
T3 - 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
SP - 777
EP - 780
BT - 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
Y2 - 9 December 2018 through 12 December 2018
ER -
