A real-time 64-monosyllable recognition LSI with learning mechanism

K. Nakamura, Qiang Zhu, S. Maruoka, T. Horiyama, S. Kimura, K. Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In the paper, a real-time 64-mono-syllable recognition LSI is presented. The LSI accepts 11.6 ms speech frame and outputs a 6-bit symbol-code for each frame by the end of the next frame in a pipelining manner. The recognition method is based on the Hidden Markov Model (HMM) and is speaker-independent. An on-chip learning mechanism has also been designed, but the circuit is off-chip for the present implementation because of the restriction of LSI area. The LSI is fabricated by VDEC Rohm with a 0.6 μm CMOS process on a 4.5 mmx4.5 mm chip.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2001
Subtitle of host publicationAsia and South Pacific Design Automation Conference 2001
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages31-32
Number of pages2
ISBN (Electronic)0780366336
DOIs
Publication statusPublished - 2001
Externally publishedYes
EventAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 - Yokohama, Japan
Duration: 2001 Jan 302001 Feb 2

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2001-January

Other

OtherAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001
Country/TerritoryJapan
CityYokohama
Period01/1/3001/2/2

Keywords

  • Adders
  • Circuits
  • Hardware
  • Hidden Markov models
  • Large scale integration
  • Learning systems
  • Linear predictive coding
  • Speech analysis
  • Speech coding
  • Speech recognition

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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