TY - GEN
T1 - A Reconfigurable Area and Energy Efficient Hardware Accelerator of Five High-order Operators for Vision Sensor Based Robot Systems
AU - Wang, Qianjin
AU - Zhan, Yi
AU - Liu, Bingqiang
AU - Wu, Jiajun
AU - Shi, Youhua
AU - Yu, Guoyi
AU - Wang, Chao
N1 - Funding Information:
ACKNOWLEDGMENT This research presented in the paper is partially supported by National Key Research & Development Program of China (2019YFB1310001). Corresponding email: yuguoyi@189.cn. REFERENCES [1] McAndrew, et.al. "An introduction to digital image processing with matlab notes for scm2511 image processing." School of Computer Science and Mathematics, Victoria University of Technology 264.1 (2004): 1-264. [2] S. Purohit, et.al. "Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications," in IEEE Trans. VLSI Systs., vol. 21, no. 7, pp. 1346-1350, July 2013. [3] D. Fronte, et.al., "Celator: A Multi-algorithm Cryptographic Co-processor," 2008 Intl. Conf. Reconfig. Comput. FPGAs, Cancun, Mexico, 2008, pp. 438-443. [4] Z. Chen, et.al., "Calculating depth image with pixel-parallel processor for a ToF image sensing system," 2015 IEEE Sensors, Busan, South Korea, 2015, pp. 1-4.
Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - This paper proposes a reconfigurable hardware accelerator design of five major high-order operators for vision sensor based robot systems. These five high-order operators include convolution, median filtering, Euclidean distance, vector inner-product and iToF, which are intensively used in robot vision algorithms. In this work, a reconfigurable hardware accelerator design method for multiple high-order operators is proposed. FPGA implementation results show that the proposed design has achieved area efficiency with 17.54% reduced LUTs and 44.02% reduced FFs against the baseline hardware design of the five high-order operators. Case studies of Laplace edge-detection and iToF benchmark demonstrate the energy efficiency of proposed design with 19.70% and 6.2% reduction in energy consumption, respectively.
AB - This paper proposes a reconfigurable hardware accelerator design of five major high-order operators for vision sensor based robot systems. These five high-order operators include convolution, median filtering, Euclidean distance, vector inner-product and iToF, which are intensively used in robot vision algorithms. In this work, a reconfigurable hardware accelerator design method for multiple high-order operators is proposed. FPGA implementation results show that the proposed design has achieved area efficiency with 17.54% reduced LUTs and 44.02% reduced FFs against the baseline hardware design of the five high-order operators. Case studies of Laplace edge-detection and iToF benchmark demonstrate the energy efficiency of proposed design with 19.70% and 6.2% reduction in energy consumption, respectively.
KW - Reconfigurable hardware
KW - robot SoC
KW - vision sensor
UR - http://www.scopus.com/inward/record.url?scp=85124802636&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85124802636&partnerID=8YFLogxK
U2 - 10.1109/ICTA53157.2021.9661719
DO - 10.1109/ICTA53157.2021.9661719
M3 - Conference contribution
AN - SCOPUS:85124802636
T3 - 2021 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2021
SP - 189
EP - 190
BT - 2021 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2021 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2021
Y2 - 24 November 2021 through 26 November 2021
ER -
