A reconfigurable processor based on ALU array architecture with limitation on the interconnection

Makoto Okada; Tatsuo Hiramatsu; Hiroshi Nakajima; Makoto Ozone; Katsunori Hirase; Shinji Kimura

doi:10.1109/IPDPS.2005.64

A reconfigurable processor based on ALU array architecture with limitation on the interconnection

Makoto Okada^*, Tatsuo Hiramatsu, Hiroshi Nakajima, Makoto Ozone, Katsunori Hirase, Shinji Kimura

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Dynamic reconfigurable processor based on ALU array architecture for consumer appliances is described. To implement reconfigurable system on portable or mobile products, we have tried to develop smaller and powerful reconfigurable processor. We have proposed the ALU array architecture with the limitation on the interconnection for area reduction. By the proposed architecture, we could reduce gate size by 63% on interconnections. Also, we have shown that the performance of proposed architecture is almost the same as one without limitations. The proposed processor is a parallel processing processor that consists of a sequencer and an ALU array, adopted multi threading technology. We have developed compilation tools from source codes written in C language for the proposed processor. We demonstrate the software model of the processor using MPEG-4 video decoding application.

Original language	English
Title of host publication	Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
Pages	152a
DOIs	https://doi.org/10.1109/IPDPS.2005.64
Publication status	Published - 2005 Dec 1
Event	19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005 - Denver, CO, United States Duration: 2005 Apr 4 → 2005 Apr 8

Publication series

Name	Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
Volume	2005

Conference

Conference	19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
Country/Territory	United States
City	Denver, CO
Period	05/4/4 → 05/4/8

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1109/IPDPS.2005.64

Cite this

Okada, M., Hiramatsu, T., Nakajima, H., Ozone, M., Hirase, K., & Kimura, S. (2005). A reconfigurable processor based on ALU array architecture with limitation on the interconnection. In Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005 (pp. 152a). [1420005] (Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005; Vol. 2005). https://doi.org/10.1109/IPDPS.2005.64

A reconfigurable processor based on ALU array architecture with limitation on the interconnection. / Okada, Makoto; Hiramatsu, Tatsuo; Nakajima, Hiroshi et al.

Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005. 2005. p. 152a 1420005 (Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Okada, M, Hiramatsu, T, Nakajima, H, Ozone, M, Hirase, K & Kimura, S 2005, A reconfigurable processor based on ALU array architecture with limitation on the interconnection. in Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005., 1420005, Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005, vol. 2005, pp. 152a, 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005, Denver, CO, United States, 05/4/4. https://doi.org/10.1109/IPDPS.2005.64

Okada M, Hiramatsu T, Nakajima H, Ozone M, Hirase K, Kimura S. A reconfigurable processor based on ALU array architecture with limitation on the interconnection. In Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005. 2005. p. 152a. 1420005. (Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005). doi: 10.1109/IPDPS.2005.64

Okada, Makoto ; Hiramatsu, Tatsuo ; Nakajima, Hiroshi et al. / A reconfigurable processor based on ALU array architecture with limitation on the interconnection. Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005. 2005. pp. 152a (Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005).

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A reconfigurable processor based on ALU array architecture with limitation on the interconnection

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