A reconfigurable processor based on ALU array architecture with limitation on the interconnection

Makoto Okada, Tatsuo Hiramatsu, Hiroshi Nakajima, Makoto Ozone, Katsunori Hirase, Shinji Kimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Dynamic reconfigurable processor based on ALU array architecture for consumer appliances is described. To implement reconfigurable system on portable or mobile products, we have tried to develop smaller and powerful reconfigurable processor. We have proposed the ALU array architecture with the limitation on the interconnection for area reduction. By the proposed architecture, we could reduce gate size by 63% on interconnections. Also, we have shown that the performance of proposed architecture is almost the same as one without limitations. The proposed processor is a parallel processing processor that consists of a sequencer and an ALU array, adopted multi threading technology. We have developed compilation tools from source codes written in C language for the proposed processor. We demonstrate the software model of the processor using MPEG-4 video decoding application.

Original languageEnglish
Title of host publicationProceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
Volume2005
DOIs
Publication statusPublished - 2005
Event19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005 - Denver, CO
Duration: 2005 Apr 42005 Apr 8

Other

Other19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
CityDenver, CO
Period05/4/405/4/8

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Decoding
Processing

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Okada, M., Hiramatsu, T., Nakajima, H., Ozone, M., Hirase, K., & Kimura, S. (2005). A reconfigurable processor based on ALU array architecture with limitation on the interconnection. In Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005 (Vol. 2005). [1420005] https://doi.org/10.1109/IPDPS.2005.64

A reconfigurable processor based on ALU array architecture with limitation on the interconnection. / Okada, Makoto; Hiramatsu, Tatsuo; Nakajima, Hiroshi; Ozone, Makoto; Hirase, Katsunori; Kimura, Shinji.

Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005. Vol. 2005 2005. 1420005.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Okada, M, Hiramatsu, T, Nakajima, H, Ozone, M, Hirase, K & Kimura, S 2005, A reconfigurable processor based on ALU array architecture with limitation on the interconnection. in Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005. vol. 2005, 1420005, 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005, Denver, CO, 05/4/4. https://doi.org/10.1109/IPDPS.2005.64
Okada M, Hiramatsu T, Nakajima H, Ozone M, Hirase K, Kimura S. A reconfigurable processor based on ALU array architecture with limitation on the interconnection. In Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005. Vol. 2005. 2005. 1420005 https://doi.org/10.1109/IPDPS.2005.64
Okada, Makoto ; Hiramatsu, Tatsuo ; Nakajima, Hiroshi ; Ozone, Makoto ; Hirase, Katsunori ; Kimura, Shinji. / A reconfigurable processor based on ALU array architecture with limitation on the interconnection. Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005. Vol. 2005 2005.
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