This paper describes an on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on the chip. The chip integrates 400 neurons and 40 000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals.
|Number of pages||8|
|Journal||IEEE Journal of Solid-State Circuits|
|Publication status||Published - 1992 Dec|
ASJC Scopus subject areas
- Electrical and Electronic Engineering