A Refreshable Analog VLSI Neural Network Chip with 400 Neurons and 40K Synapses

Yutaka Arima; Mitsuhiro Murasaki; Tsuyoshi Yamada; Atsushi Maeda; Hirofumi Shinohara

doi:10.1109/4.173115

A Refreshable Analog VLSI Neural Network Chip with 400 Neurons and 40K Synapses

Yutaka Arima, Mitsuhiro Murasaki, Tsuyoshi Yamada, Atsushi Maeda, Hirofumi Shinohara

Research output: Contribution to journal › Article › peer-review

28 Citations (Scopus)

Abstract

This paper describes an on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on the chip. The chip integrates 400 neurons and 40 000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals.

Original language	English
Pages (from-to)	1854-1861
Number of pages	8
Journal	IEEE Journal of Solid-State Circuits
Volume	27
Issue number	12
DOIs	https://doi.org/10.1109/4.173115
Publication status	Published - 1992 Dec
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/4.173115

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title = "A Refreshable Analog VLSI Neural Network Chip with 400 Neurons and 40K Synapses",

abstract = "This paper describes an on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on the chip. The chip integrates 400 neurons and 40 000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals.",

author = "Yutaka Arima and Mitsuhiro Murasaki and Tsuyoshi Yamada and Atsushi Maeda and Hirofumi Shinohara",

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AU - Shinohara, Hirofumi

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A Refreshable Analog VLSI Neural Network Chip with 400 Neurons and 40K Synapses

Abstract

ASJC Scopus subject areas

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