A refreshable analog VLSI neural network chip with 400 neurons and 40k synapses

Yutaka Arima, Mitsuhiro Murasaki, Tsuyoshi Yamada, Atushi Maeda, Hirofumi Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Describes a self-learning neural network chip with refresh on-chip analog synaptic weight storage. The chip integrates 400 neurons and 40000 synapses with 0.8μm double poly-Si double metal CMOS technology. Refresh time is less than 300 mu s. The chip retains learned information by repeating refresh at 100 ms intervals. The proposed refresh method is based on the decision made by a subnetwork. The subnetwork learns if the settling states of the main network should be memorized, retains the weights until they are relearned, and stores a 4-b representation of subnetwork weights in a counter. The main network is refreshed according to the output of the subnetwork.

Original languageEnglish
Title of host publicationDigest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages132-133
Number of pages2
ISBN (Electronic)0780305736
DOIs
Publication statusPublished - 1992 Jan 1
Externally publishedYes
Event39th IEEE International Solid-State Circuits Conference, ISSCC 1992 - San Francisco, United States
Duration: 1992 Feb 191992 Feb 21

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume1992-February
ISSN (Print)0193-6530

Conference

Conference39th IEEE International Solid-State Circuits Conference, ISSCC 1992
CountryUnited States
CitySan Francisco
Period92/2/1992/2/21

Fingerprint

Polysilicon
Neurons
Metals
Neural networks

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Arima, Y., Murasaki, M., Yamada, T., Maeda, A., & Shinohara, H. (1992). A refreshable analog VLSI neural network chip with 400 neurons and 40k synapses. In Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992 (pp. 132-133). [200447] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 1992-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.1992.200447

A refreshable analog VLSI neural network chip with 400 neurons and 40k synapses. / Arima, Yutaka; Murasaki, Mitsuhiro; Yamada, Tsuyoshi; Maeda, Atushi; Shinohara, Hirofumi.

Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992. Institute of Electrical and Electronics Engineers Inc., 1992. p. 132-133 200447 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 1992-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Arima, Y, Murasaki, M, Yamada, T, Maeda, A & Shinohara, H 1992, A refreshable analog VLSI neural network chip with 400 neurons and 40k synapses. in Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992., 200447, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 1992-February, Institute of Electrical and Electronics Engineers Inc., pp. 132-133, 39th IEEE International Solid-State Circuits Conference, ISSCC 1992, San Francisco, United States, 92/2/19. https://doi.org/10.1109/ISSCC.1992.200447
Arima Y, Murasaki M, Yamada T, Maeda A, Shinohara H. A refreshable analog VLSI neural network chip with 400 neurons and 40k synapses. In Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992. Institute of Electrical and Electronics Engineers Inc. 1992. p. 132-133. 200447. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.1992.200447
Arima, Yutaka ; Murasaki, Mitsuhiro ; Yamada, Tsuyoshi ; Maeda, Atushi ; Shinohara, Hirofumi. / A refreshable analog VLSI neural network chip with 400 neurons and 40k synapses. Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992. Institute of Electrical and Electronics Engineers Inc., 1992. pp. 132-133 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).
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