A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode

Masaki Kumanoya, Kazuyasu Fujishima, Hideshi Miyatake, Nishimura Yasumasa, Kazunori Saito, Takayuki Matsukawa, Tsutomu Yoshihara, Takao Nakano

Research output: Contribution to journalArticle

Abstract

This paper describes a single 5-V supply 1-Mbit DRAM using a half Vccbiased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.

Original languageEnglish
Pages (from-to)909-913
Number of pages5
JournalIEEE Journal of Solid-State Circuits
Volume20
Issue number5
DOIs
Publication statusPublished - 1985
Externally publishedYes

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Dynamic random access storage
Redundancy
Titanium
Electric fields
Data storage equipment
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Kumanoya, M., Fujishima, K., Miyatake, H., Yasumasa, N., Saito, K., Matsukawa, T., ... Nakano, T. (1985). A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode. IEEE Journal of Solid-State Circuits, 20(5), 909-913. https://doi.org/10.1109/JSSC.1985.1052414

A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode. / Kumanoya, Masaki; Fujishima, Kazuyasu; Miyatake, Hideshi; Yasumasa, Nishimura; Saito, Kazunori; Matsukawa, Takayuki; Yoshihara, Tsutomu; Nakano, Takao.

In: IEEE Journal of Solid-State Circuits, Vol. 20, No. 5, 1985, p. 909-913.

Research output: Contribution to journalArticle

Kumanoya, M, Fujishima, K, Miyatake, H, Yasumasa, N, Saito, K, Matsukawa, T, Yoshihara, T & Nakano, T 1985, 'A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode', IEEE Journal of Solid-State Circuits, vol. 20, no. 5, pp. 909-913. https://doi.org/10.1109/JSSC.1985.1052414
Kumanoya M, Fujishima K, Miyatake H, Yasumasa N, Saito K, Matsukawa T et al. A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode. IEEE Journal of Solid-State Circuits. 1985;20(5):909-913. https://doi.org/10.1109/JSSC.1985.1052414
Kumanoya, Masaki ; Fujishima, Kazuyasu ; Miyatake, Hideshi ; Yasumasa, Nishimura ; Saito, Kazunori ; Matsukawa, Takayuki ; Yoshihara, Tsutomu ; Nakano, Takao. / A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode. In: IEEE Journal of Solid-State Circuits. 1985 ; Vol. 20, No. 5. pp. 909-913.
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