A robust SOI SRAM architecture by using advanced ABC technology for 32nm node and beyond LSTP devices

Yuuichi Hirano, Mikio Tsujiuchi, Kozo Ishikawa, Hirofumi Shinohara, Takashi Terada, Yukio Maki, Toshiaki Iwamatsu, Katsumi Eikyu, Tetsuya Uchida, Shigeki Obayashi, Koji Nii, Yasumasa Tsukamoto, Makoto Yabuuchi, Takashi Ipposhi, Hidekazu Oda, Yasuo Inoue

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

This paper presents that Advanced Actively Body-bias Controlled (Advanced ABC) technology contributes to enhancing operation margins of SRAMs. Significant enhancement of Static Noise Margin (SNM) is successfully realized by using a body bias of load transistors while suppressing threshold-voltage variations for the first time. It is demonstrated that the write and read margins of 65nm-node SOI SRAMs are improved by the Advanced ABC technology. Furthermore, it is found that the SNM is enhanced by 27% for 32nm and 49% for 22nm node. It is summarized that this technology is one of countermeasures for emerging generations.

Original languageEnglish
Title of host publicationDigest of Technical Papers - Symposium on VLSI Technology
Pages78-79
Number of pages2
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event2007 Symposium on VLSI Technology, VLSIT 2007 - Kyoto, Japan
Duration: 2007 Jun 122007 Jun 14

Other

Other2007 Symposium on VLSI Technology, VLSIT 2007
CountryJapan
CityKyoto
Period07/6/1207/6/14

Fingerprint

Static random access storage
Threshold voltage
Transistors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Hirano, Y., Tsujiuchi, M., Ishikawa, K., Shinohara, H., Terada, T., Maki, Y., ... Inoue, Y. (2007). A robust SOI SRAM architecture by using advanced ABC technology for 32nm node and beyond LSTP devices. In Digest of Technical Papers - Symposium on VLSI Technology (pp. 78-79). [4339734] https://doi.org/10.1109/VLSIT.2007.4339734

A robust SOI SRAM architecture by using advanced ABC technology for 32nm node and beyond LSTP devices. / Hirano, Yuuichi; Tsujiuchi, Mikio; Ishikawa, Kozo; Shinohara, Hirofumi; Terada, Takashi; Maki, Yukio; Iwamatsu, Toshiaki; Eikyu, Katsumi; Uchida, Tetsuya; Obayashi, Shigeki; Nii, Koji; Tsukamoto, Yasumasa; Yabuuchi, Makoto; Ipposhi, Takashi; Oda, Hidekazu; Inoue, Yasuo.

Digest of Technical Papers - Symposium on VLSI Technology. 2007. p. 78-79 4339734.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hirano, Y, Tsujiuchi, M, Ishikawa, K, Shinohara, H, Terada, T, Maki, Y, Iwamatsu, T, Eikyu, K, Uchida, T, Obayashi, S, Nii, K, Tsukamoto, Y, Yabuuchi, M, Ipposhi, T, Oda, H & Inoue, Y 2007, A robust SOI SRAM architecture by using advanced ABC technology for 32nm node and beyond LSTP devices. in Digest of Technical Papers - Symposium on VLSI Technology., 4339734, pp. 78-79, 2007 Symposium on VLSI Technology, VLSIT 2007, Kyoto, Japan, 07/6/12. https://doi.org/10.1109/VLSIT.2007.4339734
Hirano Y, Tsujiuchi M, Ishikawa K, Shinohara H, Terada T, Maki Y et al. A robust SOI SRAM architecture by using advanced ABC technology for 32nm node and beyond LSTP devices. In Digest of Technical Papers - Symposium on VLSI Technology. 2007. p. 78-79. 4339734 https://doi.org/10.1109/VLSIT.2007.4339734
Hirano, Yuuichi ; Tsujiuchi, Mikio ; Ishikawa, Kozo ; Shinohara, Hirofumi ; Terada, Takashi ; Maki, Yukio ; Iwamatsu, Toshiaki ; Eikyu, Katsumi ; Uchida, Tetsuya ; Obayashi, Shigeki ; Nii, Koji ; Tsukamoto, Yasumasa ; Yabuuchi, Makoto ; Ipposhi, Takashi ; Oda, Hidekazu ; Inoue, Yasuo. / A robust SOI SRAM architecture by using advanced ABC technology for 32nm node and beyond LSTP devices. Digest of Technical Papers - Symposium on VLSI Technology. 2007. pp. 78-79
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AU - Maki, Yukio

AU - Iwamatsu, Toshiaki

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