A Scalability Analysis of Many Cores and On-Chip Mesh Networks on the TILE-Gx Platform

Ye Liu, Hiroshi Sasaki, Shinpei Kato, Masato Edahiro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

TILE-Gx processors that have emerged in recent years can be considered as the representative of prevailing many-core processors. The available TILE-Gx processors are featured with directory-based cache coherence protocol, two-dimensional mesh networks and up to 72 on-chip cores. In this paper, we study and analyze problems of performance scalability and network collision of many-core processors using the TILE-Gx36 processor. We find that most multi-threaded programs from the PARSEC benchmark suite, which aim at shared-memory on-chip processors, cannot scale well on Linux as the number of cores increases. Meanwhile, applications compiled with Pthreads get affected by the approach of task-to-core assignment. The results also show that current multi-threaded applications do not entirely utilize the hardware resources on TILE-Gx36 processor. Moreover, OS designers might need to pay attention to the memory allocation if memory stripping is not supported. Because huge memory accesses to only one memory controller can burden the two-dimensional mesh network. This observation appears if cores access the further memory controllers intensively as well.

Original languageEnglish
Title of host publicationProceedings - IEEE 10th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages46-52
Number of pages7
ISBN (Electronic)9781509035304
DOIs
Publication statusPublished - 2016 Dec 5
Externally publishedYes
Event10th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016 - Lyon, France
Duration: 2016 Sep 212016 Sep 23

Publication series

NameProceedings - IEEE 10th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016

Other

Other10th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016
CountryFrance
CityLyon
Period16/9/2116/9/23

Keywords

  • Many Core
  • Mesh Network
  • Scalability
  • TILEGx platform

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture

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  • Cite this

    Liu, Y., Sasaki, H., Kato, S., & Edahiro, M. (2016). A Scalability Analysis of Many Cores and On-Chip Mesh Networks on the TILE-Gx Platform. In Proceedings - IEEE 10th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016 (pp. 46-52). [7774419] (Proceedings - IEEE 10th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MCSoC.2016.40