A selector-based FFT processor and its FPGA implementation

Yuya Hirai, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    Fast Fourier transform (FFT) is used in various applications such as signal processings and developing a high-speed FFT processor is quite required. In this paper, we propose a high-speed FFT processor based on selector logics. The selector-based FFT processor is constructed by focusing on the subtract-multiplication operations and partly applying selector logics to them. Furthermore, we implement the selector-based FFT processor on a Xilinx FPGA. Experimental results show that our proposed FFT processor can improve the processing speed by up to 21% and also reduce the number of LUTs by up to 33% compared with a naive FFT processor.

    Original languageEnglish
    Title of host publicationProceedings - International SoC Design Conference 2017, ISOCC 2017
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages88-89
    Number of pages2
    ISBN (Electronic)9781538622858
    DOIs
    Publication statusPublished - 2018 May 29
    Event14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of
    Duration: 2017 Nov 52017 Nov 8

    Other

    Other14th International SoC Design Conference, ISOCC 2017
    CountryKorea, Republic of
    CitySeoul
    Period17/11/517/11/8

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    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering
    • Electronic, Optical and Magnetic Materials

    Cite this

    Hirai, Y., Kawamura, K., Yanagisawa, M., & Togawa, N. (2018). A selector-based FFT processor and its FPGA implementation. In Proceedings - International SoC Design Conference 2017, ISOCC 2017 (pp. 88-89). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2017.8368783