A simultaneous placement and global routing algorithm for FPGAs with power optimization

Nozomu Togawa, Kaoru Ukai, Masao Yanagisawa, Tatsuo Ohtsuki

    Research output: Contribution to journalArticle

    Abstract

    This paper proposes a simultaneous placement and global routing algorithm for FPGAs with power optimization. The algorithm is based on hierarchical bipartitioning of layout regions and sets of logic-blocks. When bipartitioning a layout region, pseudo-blocks are introduced to preserve connections if there exist connections between bipartitioned logic-block sets. A global route is represented by a sequence of pseudo-blocks. Since pseudo-blocks and logic-blocks can be dealt with equally, placement and global routing are processed simultaneously. The algorithm gives weights to nets with high switching probabilities and attempts to assign the blocks connected by weighted nets to the same region. Thus their length is shortened and the power consumption of a whole circuit can be reduced. The experimental results demonstrate the effectiveness and efficiency of the algorithm.

    Original languageEnglish
    Pages (from-to)99-112
    Number of pages14
    JournalJournal of Circuits, Systems and Computers
    Volume9
    Issue number1-2
    Publication statusPublished - 1999 Feb

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    Routing algorithms
    Field programmable gate arrays (FPGA)
    Electric power utilization
    Networks (circuits)

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    Cite this

    A simultaneous placement and global routing algorithm for FPGAs with power optimization. / Togawa, Nozomu; Ukai, Kaoru; Yanagisawa, Masao; Ohtsuki, Tatsuo.

    In: Journal of Circuits, Systems and Computers, Vol. 9, No. 1-2, 02.1999, p. 99-112.

    Research output: Contribution to journalArticle

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