Abstract
This paper presents an efficient architecture of finding the first two minimum values for row operation in LDPC decoding. Given a set of numbers X, efficient algorithm and its corresponding hardware implementation for finding the first minimum value, min-1st, second minimum value, min-2nd and the position of min-1st are greatly needed in LDPC decoder design. The design is based on sorting-based approach proposed in[10]. Compared to the conventional architecture, our architecture performs better in both speed and area. An extension method is also presented to apply the proposed architecture when the number of inputs is an any positive integer.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011 |
| Pages | 95-98 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2011 |
| Event | 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011 - Penang Duration: 2011 Mar 4 → 2011 Mar 6 |
Other
| Other | 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011 |
|---|---|
| City | Penang |
| Period | 11/3/4 → 11/3/6 |
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Keywords
- LDPC codes
- LDPC decoder
- min-sum algoritm
- minimum finder
- sorting-based architecture
ASJC Scopus subject areas
- Signal Processing
Cite this
A sorting-based architecture of finding the first two minimum values for LDPC decoding. / Xie, Qian; Chen, Zhixiang; Peng, Xiao; Goto, Satoshi.
Proceedings - 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011. 2011. p. 95-98 5759850.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A sorting-based architecture of finding the first two minimum values for LDPC decoding
AU - Xie, Qian
AU - Chen, Zhixiang
AU - Peng, Xiao
AU - Goto, Satoshi
PY - 2011
Y1 - 2011
N2 - This paper presents an efficient architecture of finding the first two minimum values for row operation in LDPC decoding. Given a set of numbers X, efficient algorithm and its corresponding hardware implementation for finding the first minimum value, min-1st, second minimum value, min-2nd and the position of min-1st are greatly needed in LDPC decoder design. The design is based on sorting-based approach proposed in[10]. Compared to the conventional architecture, our architecture performs better in both speed and area. An extension method is also presented to apply the proposed architecture when the number of inputs is an any positive integer.
AB - This paper presents an efficient architecture of finding the first two minimum values for row operation in LDPC decoding. Given a set of numbers X, efficient algorithm and its corresponding hardware implementation for finding the first minimum value, min-1st, second minimum value, min-2nd and the position of min-1st are greatly needed in LDPC decoder design. The design is based on sorting-based approach proposed in[10]. Compared to the conventional architecture, our architecture performs better in both speed and area. An extension method is also presented to apply the proposed architecture when the number of inputs is an any positive integer.
KW - LDPC codes
KW - LDPC decoder
KW - min-sum algoritm
KW - minimum finder
KW - sorting-based architecture
UR - http://www.scopus.com/inward/record.url?scp=79957513334&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79957513334&partnerID=8YFLogxK
U2 - 10.1109/CSPA.2011.5759850
DO - 10.1109/CSPA.2011.5759850
M3 - Conference contribution
SN - 9781612844145
SP - 95
EP - 98
BT - Proceedings - 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011
ER -