A sorting-based architecture of finding the first two minimum values for LDPC decoding

Qian Xie; Zhixiang Chen; Xiao Peng; Satoshi Goto

doi:10.1109/CSPA.2011.5759850

A sorting-based architecture of finding the first two minimum values for LDPC decoding

Qian Xie^*, Zhixiang Chen, Xiao Peng, Satoshi Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

This paper presents an efficient architecture of finding the first two minimum values for row operation in LDPC decoding. Given a set of numbers X, efficient algorithm and its corresponding hardware implementation for finding the first minimum value, min-1st, second minimum value, min-2nd and the position of min-1st are greatly needed in LDPC decoder design. The design is based on sorting-based approach proposed in[10]. Compared to the conventional architecture, our architecture performs better in both speed and area. An extension method is also presented to apply the proposed architecture when the number of inputs is an any positive integer.

Original language	English
Title of host publication	Proceedings - 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011
Pages	95-98
Number of pages	4
DOIs	https://doi.org/10.1109/CSPA.2011.5759850
Publication status	Published - 2011
Event	2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011 - Penang Duration: 2011 Mar 4 → 2011 Mar 6

Other

Other	2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011
City	Penang
Period	11/3/4 → 11/3/6

Keywords

LDPC codes
LDPC decoder
min-sum algoritm
minimum finder
sorting-based architecture

ASJC Scopus subject areas

Signal Processing

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10.1109/CSPA.2011.5759850

Cite this

Xie, Q, Chen, Z, Peng, X & Goto, S 2011, A sorting-based architecture of finding the first two minimum values for LDPC decoding. in Proceedings - 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011., 5759850, pp. 95-98, 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011, Penang, 11/3/4. https://doi.org/10.1109/CSPA.2011.5759850

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title = "A sorting-based architecture of finding the first two minimum values for LDPC decoding",

abstract = "This paper presents an efficient architecture of finding the first two minimum values for row operation in LDPC decoding. Given a set of numbers X, efficient algorithm and its corresponding hardware implementation for finding the first minimum value, min-1st, second minimum value, min-2nd and the position of min-1st are greatly needed in LDPC decoder design. The design is based on sorting-based approach proposed in[10]. Compared to the conventional architecture, our architecture performs better in both speed and area. An extension method is also presented to apply the proposed architecture when the number of inputs is an any positive integer.",

keywords = "LDPC codes, LDPC decoder, min-sum algoritm, minimum finder, sorting-based architecture",

author = "Qian Xie and Zhixiang Chen and Xiao Peng and Satoshi Goto",

year = "2011",

doi = "10.1109/CSPA.2011.5759850",

language = "English",

isbn = "9781612844145",

pages = "95--98",

booktitle = "Proceedings - 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011",

note = "2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011 ; Conference date: 04-03-2011 Through 06-03-2011",

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AU - Xie, Qian

AU - Chen, Zhixiang

AU - Peng, Xiao

AU - Goto, Satoshi

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N2 - This paper presents an efficient architecture of finding the first two minimum values for row operation in LDPC decoding. Given a set of numbers X, efficient algorithm and its corresponding hardware implementation for finding the first minimum value, min-1st, second minimum value, min-2nd and the position of min-1st are greatly needed in LDPC decoder design. The design is based on sorting-based approach proposed in[10]. Compared to the conventional architecture, our architecture performs better in both speed and area. An extension method is also presented to apply the proposed architecture when the number of inputs is an any positive integer.

AB - This paper presents an efficient architecture of finding the first two minimum values for row operation in LDPC decoding. Given a set of numbers X, efficient algorithm and its corresponding hardware implementation for finding the first minimum value, min-1st, second minimum value, min-2nd and the position of min-1st are greatly needed in LDPC decoder design. The design is based on sorting-based approach proposed in[10]. Compared to the conventional architecture, our architecture performs better in both speed and area. An extension method is also presented to apply the proposed architecture when the number of inputs is an any positive integer.

KW - LDPC codes

KW - LDPC decoder

KW - min-sum algoritm

KW - minimum finder

KW - sorting-based architecture

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DO - 10.1109/CSPA.2011.5759850

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BT - Proceedings - 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011

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Y2 - 4 March 2011 through 6 March 2011

ER -

A sorting-based architecture of finding the first two minimum values for LDPC decoding

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Keywords

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