A sorting-based architecture of finding the first two minimum values for LDPC decoding

Qian Xie, Zhixiang Chen, Xiao Peng, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

This paper presents an efficient architecture of finding the first two minimum values for row operation in LDPC decoding. Given a set of numbers X, efficient algorithm and its corresponding hardware implementation for finding the first minimum value, min-1st, second minimum value, min-2nd and the position of min-1st are greatly needed in LDPC decoder design. The design is based on sorting-based approach proposed in[10]. Compared to the conventional architecture, our architecture performs better in both speed and area. An extension method is also presented to apply the proposed architecture when the number of inputs is an any positive integer.

Original languageEnglish
Title of host publicationProceedings - 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011
Pages95-98
Number of pages4
DOIs
Publication statusPublished - 2011
Event2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011 - Penang
Duration: 2011 Mar 42011 Mar 6

Other

Other2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011
CityPenang
Period11/3/411/3/6

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Keywords

  • LDPC codes
  • LDPC decoder
  • min-sum algoritm
  • minimum finder
  • sorting-based architecture

ASJC Scopus subject areas

  • Signal Processing

Cite this

Xie, Q., Chen, Z., Peng, X., & Goto, S. (2011). A sorting-based architecture of finding the first two minimum values for LDPC decoding. In Proceedings - 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011 (pp. 95-98). [5759850] https://doi.org/10.1109/CSPA.2011.5759850