A standard cell optimization method for near-threshold voltage operations

Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Near-threshold voltage operation is a well-known solution for drastically improving the energy efficiency of microprocessors fabricated with the latest process technologies. However, it is not well studied how the optimal gate size of standard cells changes when the supply voltage of the microprocessors gets closer to the threshold voltage. This paper first shows an experimental observation that the optimal gate size for nearthreshold voltage which is 0.6V in this work is far from the optimal gate size for the nominal supply voltage which is 1.2V in our target process technology. Based on this fact, the paper next presents our cell optimization flow which finds the optimal gate sizes of individual standard cells operating at the near-threshold voltage. The experimental results show that, when operating at the 0.6V condition, the energy consumptions of several benchmark circuits synthesized with our standard cells optimized for the 0.6V condition can be reduced by 31% at the best case and by 23% on average compared with those of the same circuits synthesized with the cells optimized for the nominal supply voltage.

Original languageEnglish
Title of host publicationIntegrated Circuit and System Design
Subtitle of host publicationPower and Timing Modeling, Optimization and Simulation - 22nd International Workshop, PATMOS 2012, Revised Selected Papers
Pages32-41
Number of pages10
DOIs
Publication statusPublished - 2013
Externally publishedYes
Event22nd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2012 - Newcastle upon Tyne, United Kingdom
Duration: 2012 Sep 42012 Sep 6

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume7606 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference22nd International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2012
Country/TerritoryUnited Kingdom
CityNewcastle upon Tyne
Period12/9/412/9/6

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

Fingerprint

Dive into the research topics of 'A standard cell optimization method for near-threshold voltage operations'. Together they form a unique fingerprint.

Cite this