A study of sense-voltage margins in low-voltage-operating embedded DRAM macros

Akira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara

    Research output: Contribution to journalArticle

    Abstract

    The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-μm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.

    Original languageEnglish
    Pages (from-to)2020-2026
    Number of pages7
    JournalIEICE Transactions on Electronics
    VolumeE88-C
    Issue number10
    DOIs
    Publication statusPublished - 2005 Oct

    Keywords

    • DRAM
    • Embedded memory
    • Low voltage
    • System on chip
    • Voltage margin

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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  • Cite this

    Yamazaki, A., Morishita, F., Watanabe, N., Amano, T., Haraguchi, M., Noda, H., Hachisuka, A., Dosaka, K., Arimoto, K., Wake, S., Ozaki, H., & Yoshihara, T. (2005). A study of sense-voltage margins in low-voltage-operating embedded DRAM macros. IEICE Transactions on Electronics, E88-C(10), 2020-2026. https://doi.org/10.1093/ietele/e88-c.10.2020