A study of sense-voltage margins in low-voltage-operating embedded DRAM macros

Akira Yamazaki; Fukashi Morishita; Naoya Watanabe; Teruhiko Amano; Masaru Haraguchi; Hideyuki Noda; Atsushi Hachisuka; Katsumi Dosaka; Kazutami Arimoto; Setsuo Wake; Hideyuki Ozaki; Tsutomu Yoshihara

doi:10.1093/ietele/e88-c.10.2020

A study of sense-voltage margins in low-voltage-operating embedded DRAM macros

Akira Yamazaki^*, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-μm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.

Original language	English
Pages (from-to)	2020-2026
Number of pages	7
Journal	IEICE Transactions on Electronics
Volume	E88-C
Issue number	10
DOIs	https://doi.org/10.1093/ietele/e88-c.10.2020
Publication status	Published - 2005 Oct

Keywords

DRAM
Embedded memory
Low voltage
System on chip
Voltage margin

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1093/ietele/e88-c.10.2020

Cite this

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abstract = "The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-μm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.",

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AU - Yamazaki, Akira

AU - Morishita, Fukashi

AU - Watanabe, Naoya

AU - Amano, Teruhiko

AU - Haraguchi, Masaru

AU - Noda, Hideyuki

AU - Hachisuka, Atsushi

AU - Dosaka, Katsumi

AU - Arimoto, Kazutami

AU - Wake, Setsuo

AU - Ozaki, Hideyuki

AU - Yoshihara, Tsutomu

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N2 - The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-μm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.

AB - The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-μm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.

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KW - Embedded memory

KW - Low voltage

KW - System on chip

KW - Voltage margin

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A study of sense-voltage margins in low-voltage-operating embedded DRAM macros

Abstract

Keywords

ASJC Scopus subject areas

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