A thermal-aware high-level synthesis algorithm for RDR architectures through binding and allocation

    Research output: Contribution to journalArticle

    1 Citation (Scopus)

    Abstract

    With process technology scaling, a heat problem in ICs is becoming a serious issue. Since high temperature adversely impacts on reliability, design costs, and leakage power, it is necessary to incorporate thermal-aware synthesis into IC design flows. In particular, hot spots are serious concerns where a chip is locally too much heated and reducing the peak temperature inside a chip is very important. On the other hand, increasing the average interconnect delays is also becoming a serious issue. By using RDR architectures (Regular-Distributed-Register architectures), the interconnect delays can be easily estimated and their influence can be much reduced even in high-level synthesis. In this paper, we propose a thermal-aware high-level synthesis algorithm for RDR architectures. The RDR architecture divides the entire chip into islands and each island has uniform area. Our algorithm balances the energy consumption among islands through re-binding to functional units. By allocating some new additional functional units to vacant areas on islands, our algorithm further balances the energy consumption among islands and thus reduces the peak temperature. Experimental results demonstrate that our algorithm reduces the peak temperature by up to 9.1% compared with the conventional approach.

    Original languageEnglish
    Pages (from-to)312-321
    Number of pages10
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE96-A
    Issue number1
    DOIs
    Publication statusPublished - 2013 Jan

    Fingerprint

    High-level Synthesis
    Chip
    Interconnect
    Energy Consumption
    Energy utilization
    Heat problems
    Temperature
    Unit
    Hot Spot
    Leakage
    Divides
    Heat
    Entire
    Scaling
    Synthesis
    Necessary
    Architecture
    Hot Temperature
    High level synthesis
    Costs

    Keywords

    • High-level synthesis
    • Hot spots
    • Interconnect delays
    • RDR
    • Thermal-aware

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Graphics and Computer-Aided Design
    • Applied Mathematics
    • Signal Processing

    Cite this

    @article{0881d185fced4ccd93162b6532a0180b,
    title = "A thermal-aware high-level synthesis algorithm for RDR architectures through binding and allocation",
    abstract = "With process technology scaling, a heat problem in ICs is becoming a serious issue. Since high temperature adversely impacts on reliability, design costs, and leakage power, it is necessary to incorporate thermal-aware synthesis into IC design flows. In particular, hot spots are serious concerns where a chip is locally too much heated and reducing the peak temperature inside a chip is very important. On the other hand, increasing the average interconnect delays is also becoming a serious issue. By using RDR architectures (Regular-Distributed-Register architectures), the interconnect delays can be easily estimated and their influence can be much reduced even in high-level synthesis. In this paper, we propose a thermal-aware high-level synthesis algorithm for RDR architectures. The RDR architecture divides the entire chip into islands and each island has uniform area. Our algorithm balances the energy consumption among islands through re-binding to functional units. By allocating some new additional functional units to vacant areas on islands, our algorithm further balances the energy consumption among islands and thus reduces the peak temperature. Experimental results demonstrate that our algorithm reduces the peak temperature by up to 9.1{\%} compared with the conventional approach.",
    keywords = "High-level synthesis, Hot spots, Interconnect delays, RDR, Thermal-aware",
    author = "Kazushi Kawamura and Masao Yanagisawa and Nozomu Togawa",
    year = "2013",
    month = "1",
    doi = "10.1587/transfun.E96.A.312",
    language = "English",
    volume = "E96-A",
    pages = "312--321",
    journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
    issn = "0916-8508",
    publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
    number = "1",

    }

    TY - JOUR

    T1 - A thermal-aware high-level synthesis algorithm for RDR architectures through binding and allocation

    AU - Kawamura, Kazushi

    AU - Yanagisawa, Masao

    AU - Togawa, Nozomu

    PY - 2013/1

    Y1 - 2013/1

    N2 - With process technology scaling, a heat problem in ICs is becoming a serious issue. Since high temperature adversely impacts on reliability, design costs, and leakage power, it is necessary to incorporate thermal-aware synthesis into IC design flows. In particular, hot spots are serious concerns where a chip is locally too much heated and reducing the peak temperature inside a chip is very important. On the other hand, increasing the average interconnect delays is also becoming a serious issue. By using RDR architectures (Regular-Distributed-Register architectures), the interconnect delays can be easily estimated and their influence can be much reduced even in high-level synthesis. In this paper, we propose a thermal-aware high-level synthesis algorithm for RDR architectures. The RDR architecture divides the entire chip into islands and each island has uniform area. Our algorithm balances the energy consumption among islands through re-binding to functional units. By allocating some new additional functional units to vacant areas on islands, our algorithm further balances the energy consumption among islands and thus reduces the peak temperature. Experimental results demonstrate that our algorithm reduces the peak temperature by up to 9.1% compared with the conventional approach.

    AB - With process technology scaling, a heat problem in ICs is becoming a serious issue. Since high temperature adversely impacts on reliability, design costs, and leakage power, it is necessary to incorporate thermal-aware synthesis into IC design flows. In particular, hot spots are serious concerns where a chip is locally too much heated and reducing the peak temperature inside a chip is very important. On the other hand, increasing the average interconnect delays is also becoming a serious issue. By using RDR architectures (Regular-Distributed-Register architectures), the interconnect delays can be easily estimated and their influence can be much reduced even in high-level synthesis. In this paper, we propose a thermal-aware high-level synthesis algorithm for RDR architectures. The RDR architecture divides the entire chip into islands and each island has uniform area. Our algorithm balances the energy consumption among islands through re-binding to functional units. By allocating some new additional functional units to vacant areas on islands, our algorithm further balances the energy consumption among islands and thus reduces the peak temperature. Experimental results demonstrate that our algorithm reduces the peak temperature by up to 9.1% compared with the conventional approach.

    KW - High-level synthesis

    KW - Hot spots

    KW - Interconnect delays

    KW - RDR

    KW - Thermal-aware

    UR - http://www.scopus.com/inward/record.url?scp=84871903047&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=84871903047&partnerID=8YFLogxK

    U2 - 10.1587/transfun.E96.A.312

    DO - 10.1587/transfun.E96.A.312

    M3 - Article

    AN - SCOPUS:84871903047

    VL - E96-A

    SP - 312

    EP - 321

    JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    SN - 0916-8508

    IS - 1

    ER -