A thread partitioning algorithm in low power high-level synthesis

Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)

    Abstract

    This paper proposes a thread partitioning algorithm in low power high-level synthesis. The algorithm is applied to high-level synthesis systems. In the systems, we can describe parallel behaving circuit blocks (threads) explicitly. First it focuses on a local register file RF in a thread. It partitions a thread into two sub-threads, one of which has RF and the other does not have RF. The partitioned sub-threads need to be synchronized with each other to keep the data dependency of the original thread. Since the partitioned sub-threads have waiting time for synchronization, gated clocks can be applied to each sub-thread. Then we can synthesize a low power circuit with a low area overhead, compared to the original circuit. Experimental results demonstrate effectiveness and efficiency of the algorithm.

    Original languageEnglish
    Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
    Pages74-79
    Number of pages6
    Publication statusPublished - 2004
    EventProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama
    Duration: 2004 Jan 272004 Jan 30

    Other

    OtherProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
    CityYokohama
    Period04/1/2704/1/30

    Fingerprint

    Networks (circuits)
    Clocks
    Synchronization
    High level synthesis

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    Uchida, J., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2004). A thread partitioning algorithm in low power high-level synthesis. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 74-79)

    A thread partitioning algorithm in low power high-level synthesis. / Uchida, Jumpei; Togawa, Nozomu; Yanagisawa, Masao; Ohtsuki, Tatsuo.

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2004. p. 74-79.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Uchida, J, Togawa, N, Yanagisawa, M & Ohtsuki, T 2004, A thread partitioning algorithm in low power high-level synthesis. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. pp. 74-79, Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004, Yokohama, 04/1/27.
    Uchida J, Togawa N, Yanagisawa M, Ohtsuki T. A thread partitioning algorithm in low power high-level synthesis. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2004. p. 74-79
    Uchida, Jumpei ; Togawa, Nozomu ; Yanagisawa, Masao ; Ohtsuki, Tatsuo. / A thread partitioning algorithm in low power high-level synthesis. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2004. pp. 74-79
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