A two-level cache design space exploration system for embedded applications

Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Research output: Contribution to journalArticle

    Abstract

    Recently, two-level cache, L1 cache and L2 cache, is commonly used in a processor. Particularly in an embedded system whereby a single application or a class of applications is repeatedly executed on a processor, its cache configuration can be customized such that an optimal one is achieved. An optimal two-level cache configuration can be obtained which minimizes overall memory access time or memory energy consumption by varying the three cache parameters: the number of sets, a line size, and an associativity, for L1 cache and L2 cache. In this paper, we first extend the L1 cache simulation algorithm so that we can explore two-level cache configuration. Second, we propose two-level cache design space exploration algorithms: CRCB-T1 and CRCB-T2, each of which is based on applying Cache Inclusion Property to two-level cache configuration. Each of the proposed algorithms realizes exact cache simulation but decreases the number of cache hit/miss judgments by a factor of several thousands. Experimental results show that, by using our approach, the number of cache hit/miss judgments required to optimize a cache configurations is reduced to 1/50-1/5500 compared to the exhaustive approach. As a result, our proposed approach totally runs an average of 1398.25 times faster compared to the exhaustive approach. Our proposed cache simulation approach achieves the world fastest two-level cache design space exploration.

    Original languageEnglish
    Pages (from-to)3238-3247
    Number of pages10
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE92-A
    Issue number12
    DOIs
    Publication statusPublished - 2009 Dec

    Fingerprint

    Design Space Exploration
    Cache
    Data storage equipment
    Embedded systems
    Energy utilization
    Configuration
    Hits
    Simulation

    Keywords

    • Cache optimization
    • Cache simulation
    • Design space exploration
    • Embedded system
    • L1/L2
    • Two-level cache

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Graphics and Computer-Aided Design
    • Applied Mathematics
    • Signal Processing

    Cite this

    A two-level cache design space exploration system for embedded applications. / Tojo, Nobuaki; Togawa, Nozomu; Yanagisawa, Masao; Ohtsuki, Tatsuo.

    In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E92-A, No. 12, 12.2009, p. 3238-3247.

    Research output: Contribution to journalArticle

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