A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter

Shuai Shao, Youhua Shi, Wentao Dai, Jianyi Meng, Weiwei Shan

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    A universal delay monitor used to imitate the real critical paths is developed for variation resilient integrated circuit. This monitor is constructed based on the different proportion of logic cells and interconnects. The delay of the monitor is detected by a time-to-digital converter which keeps the sampling results precise. To reduce the deviation of the sampling results caused by PVT, a novel time-to-digital converter with self-calibration mechanism is developed. This variation resilient method based adaptive voltage scaling is applied on an ARM7 based System on a Chip on 0.18 μm CMOS process with a 112M signoff frequency and an area of 1.3∗1.3 mm2. The simulation results show that it has a 43.42% gain of power consumption under FF corner, -25°C compared to the fixed 1.8 V traditional design.

    Original languageEnglish
    Title of host publicationProceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages126-129
    Number of pages4
    ISBN (Print)9781479983636
    DOIs
    Publication statusPublished - 2015 Sep 30
    Event11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 - Singapore, Singapore
    Duration: 2015 Jun 12015 Jun 4

    Other

    Other11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
    CountrySingapore
    CitySingapore
    Period15/6/115/6/4

    Keywords

    • Adaptive voltage scaling
    • time-to-digital converter
    • universal delay monitor
    • variation resilient

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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  • Cite this

    Shao, S., Shi, Y., Dai, W., Meng, J., & Shan, W. (2015). A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter. In Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 (pp. 126-129). [7285066] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2015.7285066