A Variable Bitline Data Cache for low power design

Jiongyao Ye, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Reducing the power consumption is one of the most important design problems at present. Modern microprocessors employ caches to bridge the great speed variance between the main memory and the central processing unit, but these caches propose larger and larger proportion in the total power consumption. In fact, many values rarely need the full-bit dynamic range supported by a cache. The Narrow-Width Value (NWV) occupies a large portion of cache access and storage. It is unreasonable that the storage space for value of any data width is the same in the cache, even if NWV needs only a few bits to be stored. This paper proposes a Variable Bitline Data Cache (VBDC) which exploits the popularity of NWV stored in the cache. In VBDC design, the cache data array is divided into several sub-arrays to adapt each data pattern with the different bitline length to access. The VBDC can shut off the corresponding unused high arrays to reduce its dynamic and static power consumption. The VBDC achieves low power consumption through reducing the bitline length. Experimental results employing SPEC 2000 benchmarks show that our proposed VBDC can reduce both the dynamic power consumption ant the static power consumption by 44.75% and 42.86%.

Original languageEnglish
Title of host publicationPrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics
Pages174-177
Number of pages4
DOIs
Publication statusPublished - 2010
Event2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010 - Shanghai
Duration: 2010 Sep 222010 Sep 24

Other

Other2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010
CityShanghai
Period10/9/2210/9/24

Fingerprint

Electric power utilization
Program processors
Microprocessor chips
Data storage equipment

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Ye, J., & Watanabe, T. (2010). A Variable Bitline Data Cache for low power design. In PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (pp. 174-177). [5604932] https://doi.org/10.1109/PRIMEASIA.2010.5604932

A Variable Bitline Data Cache for low power design. / Ye, Jiongyao; Watanabe, Takahiro.

PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics. 2010. p. 174-177 5604932.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ye, J & Watanabe, T 2010, A Variable Bitline Data Cache for low power design. in PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics., 5604932, pp. 174-177, 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010, Shanghai, 10/9/22. https://doi.org/10.1109/PRIMEASIA.2010.5604932
Ye J, Watanabe T. A Variable Bitline Data Cache for low power design. In PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics. 2010. p. 174-177. 5604932 https://doi.org/10.1109/PRIMEASIA.2010.5604932
Ye, Jiongyao ; Watanabe, Takahiro. / A Variable Bitline Data Cache for low power design. PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics. 2010. pp. 174-177
@inproceedings{07190c67beb44504914bf2040dda619c,
title = "A Variable Bitline Data Cache for low power design",
abstract = "Reducing the power consumption is one of the most important design problems at present. Modern microprocessors employ caches to bridge the great speed variance between the main memory and the central processing unit, but these caches propose larger and larger proportion in the total power consumption. In fact, many values rarely need the full-bit dynamic range supported by a cache. The Narrow-Width Value (NWV) occupies a large portion of cache access and storage. It is unreasonable that the storage space for value of any data width is the same in the cache, even if NWV needs only a few bits to be stored. This paper proposes a Variable Bitline Data Cache (VBDC) which exploits the popularity of NWV stored in the cache. In VBDC design, the cache data array is divided into several sub-arrays to adapt each data pattern with the different bitline length to access. The VBDC can shut off the corresponding unused high arrays to reduce its dynamic and static power consumption. The VBDC achieves low power consumption through reducing the bitline length. Experimental results employing SPEC 2000 benchmarks show that our proposed VBDC can reduce both the dynamic power consumption ant the static power consumption by 44.75{\%} and 42.86{\%}.",
author = "Jiongyao Ye and Takahiro Watanabe",
year = "2010",
doi = "10.1109/PRIMEASIA.2010.5604932",
language = "English",
isbn = "9781424467372",
pages = "174--177",
booktitle = "PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics",

}

TY - GEN

T1 - A Variable Bitline Data Cache for low power design

AU - Ye, Jiongyao

AU - Watanabe, Takahiro

PY - 2010

Y1 - 2010

N2 - Reducing the power consumption is one of the most important design problems at present. Modern microprocessors employ caches to bridge the great speed variance between the main memory and the central processing unit, but these caches propose larger and larger proportion in the total power consumption. In fact, many values rarely need the full-bit dynamic range supported by a cache. The Narrow-Width Value (NWV) occupies a large portion of cache access and storage. It is unreasonable that the storage space for value of any data width is the same in the cache, even if NWV needs only a few bits to be stored. This paper proposes a Variable Bitline Data Cache (VBDC) which exploits the popularity of NWV stored in the cache. In VBDC design, the cache data array is divided into several sub-arrays to adapt each data pattern with the different bitline length to access. The VBDC can shut off the corresponding unused high arrays to reduce its dynamic and static power consumption. The VBDC achieves low power consumption through reducing the bitline length. Experimental results employing SPEC 2000 benchmarks show that our proposed VBDC can reduce both the dynamic power consumption ant the static power consumption by 44.75% and 42.86%.

AB - Reducing the power consumption is one of the most important design problems at present. Modern microprocessors employ caches to bridge the great speed variance between the main memory and the central processing unit, but these caches propose larger and larger proportion in the total power consumption. In fact, many values rarely need the full-bit dynamic range supported by a cache. The Narrow-Width Value (NWV) occupies a large portion of cache access and storage. It is unreasonable that the storage space for value of any data width is the same in the cache, even if NWV needs only a few bits to be stored. This paper proposes a Variable Bitline Data Cache (VBDC) which exploits the popularity of NWV stored in the cache. In VBDC design, the cache data array is divided into several sub-arrays to adapt each data pattern with the different bitline length to access. The VBDC can shut off the corresponding unused high arrays to reduce its dynamic and static power consumption. The VBDC achieves low power consumption through reducing the bitline length. Experimental results employing SPEC 2000 benchmarks show that our proposed VBDC can reduce both the dynamic power consumption ant the static power consumption by 44.75% and 42.86%.

UR - http://www.scopus.com/inward/record.url?scp=78650162122&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=78650162122&partnerID=8YFLogxK

U2 - 10.1109/PRIMEASIA.2010.5604932

DO - 10.1109/PRIMEASIA.2010.5604932

M3 - Conference contribution

AN - SCOPUS:78650162122

SN - 9781424467372

SP - 174

EP - 177

BT - PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics

ER -