A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC

Jinjia Zhou, Dajiang Zhou, Shuping Zhang, Shinji Kimura, Satoshi Goto

Research output: Contribution to journalArticle

Abstract

The next-generation 8K ultra-high-definition video format involves an extremely high bit rate, which imposes a high throughput requirement on the entropy decoder component of a video decoder. Context adaptive binary arithmetic coding (CABAC) is the entropy coding tool in the latest video coding standards including H.265/High Efficiency Video Coding and H.264/Advanced Video Coding. Due to critical data dependencies at the algorithm level, a CABAC decoder is difficult to be accelerated by simply leveraging parallelism and pipelining. This letter presents a new very-large-scale integration arithmetic decoder, which is the most critical bottleneck in CABAC decoding. Our design features a variable-clock-cycle-path architecture that exploits the differences in critical path delay and in probability of occurrence between various types of binary symbols (bins). The proposed design also incorporates a novel data-forwarding technique (rLPS forwarding) and a fast path-selection technique (coarse bin type decision), and is enhanced with the capability of processing additional bypass bins. As a result, its maximum throughput achieves 1010 Mbins/s in 90-nm CMOS, when decoding 0.96 bin per clock cycle at a maximum clock rate of 1053 MHz, which outperforms previous works by 19.1%.

Original languageEnglish
Article number7577726
Pages (from-to)556-560
Number of pages5
JournalIEEE Transactions on Circuits and Systems for Video Technology
Volume28
Issue number2
DOIs
Publication statusPublished - 2018 Feb 1

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Bins
Clocks
Image coding
Decoding
Entropy
Throughput
VLSI circuits
Processing

Keywords

  • Arithmetic decoder
  • context adaptive binary arithmetic coding (CABAC)
  • H.265
  • High Efficiency Video Coding (HEVC)

ASJC Scopus subject areas

  • Media Technology
  • Electrical and Electronic Engineering

Cite this

A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC. / Zhou, Jinjia; Zhou, Dajiang; Zhang, Shuping; Kimura, Shinji; Goto, Satoshi.

In: IEEE Transactions on Circuits and Systems for Video Technology, Vol. 28, No. 2, 7577726, 01.02.2018, p. 556-560.

Research output: Contribution to journalArticle

Zhou, Jinjia ; Zhou, Dajiang ; Zhang, Shuping ; Kimura, Shinji ; Goto, Satoshi. / A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC. In: IEEE Transactions on Circuits and Systems for Video Technology. 2018 ; Vol. 28, No. 2. pp. 556-560.
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