A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for h.264/avc

Shen Li, Xianghui Wei, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

The intra-frame coding in H.264/AVC has made significant contribution to the enhancement of coding efficiency. However it brings about a heavy computation burden in the rate distortion based (RD) mode decision (MD) process. Although the real-time encoding of 1280-720p signals is realized in recent works with existing algorithms, for higher resolution e.g. 1920-1088p some hardware-oriented fast algorithms are necessary. Yet so far few of the many proposed fast MD algorithms have seen successful hardware implementation. This paper presents a novel VLSI design (15.8k gates@200MHz, with TSMC CMOS 0.18m technology) of an edge based fast intra MD algorithm which can constantly reduce about 66% of the RD related computation with a negligible quality loss. It is expected to be utilized as a favorable accelerator hardware module in a real-time HDTV (1920-1088p) H.264 encoder or MPEG2-H.264 transcoder.

Original languageEnglish
Title of host publicationProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Pages20-24
Number of pages5
DOIs
Publication statusPublished - 2007
Event17th Great Lakes Symposium on VLSI, GLSVLSI'07 - Stresa-Lago Maggiore
Duration: 2007 Mar 112007 Mar 13

Other

Other17th Great Lakes Symposium on VLSI, GLSVLSI'07
CityStresa-Lago Maggiore
Period07/3/1107/3/13

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Hardware
High definition television
Particle accelerators

Keywords

  • Fast intra prediction mode decision
  • H.264
  • VLSI architecture

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Li, S., Wei, X., Ikenaga, T., & Goto, S. (2007). A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for h.264/avc. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI (pp. 20-24). [1228795] https://doi.org/10.1145/1228784.1228795

A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for h.264/avc. / Li, Shen; Wei, Xianghui; Ikenaga, Takeshi; Goto, Satoshi.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2007. p. 20-24 1228795.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Li, S, Wei, X, Ikenaga, T & Goto, S 2007, A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for h.264/avc. in Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI., 1228795, pp. 20-24, 17th Great Lakes Symposium on VLSI, GLSVLSI'07, Stresa-Lago Maggiore, 07/3/11. https://doi.org/10.1145/1228784.1228795
Li S, Wei X, Ikenaga T, Goto S. A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for h.264/avc. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2007. p. 20-24. 1228795 https://doi.org/10.1145/1228784.1228795
Li, Shen ; Wei, Xianghui ; Ikenaga, Takeshi ; Goto, Satoshi. / A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for h.264/avc. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2007. pp. 20-24
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