A VLSI architecture for variable block size motion estimation in H.264/AVC with low cost memory organization

Yang Song, Zhenyu Liu, Takeshi Ikenaga, Satoshi Goto

Research output: Contribution to journalArticle

14 Citations (Scopus)

Abstract

A one-dimensional (1-D) full search variable block size motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the addition operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is used to store the search area data. The design is realized in TSMC 0.18 μm 1P6M technology with a hardware cost of 67.6K gates. In typical working conditions (1.8 V, 25°C), a clock frequency of 266 MHz can be achieved.

Original languageEnglish
Pages (from-to)3594-3601
Number of pages8
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE89-A
Issue number12
DOIs
Publication statusPublished - 2006 Dec

Fingerprint

VLSI Architecture
Static random access storage
Motion Estimation
Motion estimation
Clocks
Scheduling
Hardware
Data storage equipment
Partial Sums
Work Flow
Costs
Logic
Architecture
Design

Keywords

  • H.264/AVC
  • Memory organization
  • Variable block size motion estimation (VBSME)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Information Systems

Cite this

A VLSI architecture for variable block size motion estimation in H.264/AVC with low cost memory organization. / Song, Yang; Liu, Zhenyu; Ikenaga, Takeshi; Goto, Satoshi.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E89-A, No. 12, 12.2006, p. 3594-3601.

Research output: Contribution to journalArticle

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