A VLSI architecture for variable block size motion estimation in H.264/AVC with low cost memory organization

Yang Song, Zhenyu Liu, Takeshi Ikenaga, Satoshi Goto

Research output: Contribution to journalArticlepeer-review

14 Citations (Scopus)

Abstract

A one-dimensional (1-D) full search variable block size motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the addition operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is used to store the search area data. The design is realized in TSMC 0.18 μm 1P6M technology with a hardware cost of 67.6K gates. In typical working conditions (1.8 V, 25°C), a clock frequency of 266 MHz can be achieved.

Original languageEnglish
Pages (from-to)3594-3601
Number of pages8
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE89-A
Issue number12
DOIs
Publication statusPublished - 2006 Dec

Keywords

  • H.264/AVC
  • Memory organization
  • Variable block size motion estimation (VBSME)

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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