### Abstract

Many parallel Fast Fourier Transform (FFT) algorithms adopt multiple stages architecture to increase performance. However, data permutation between stages consumes volume memory and processing time. An FFT array processing mapping algorithm is proposed in this paper to overcome this demerit. In this algorithm, arbitrary 2^{k} butterfly units (BUs) could be scheduled to work in parallel on n=2^{s}data (k=0, 1, ..., s-1). Because no inter stage data transfer is required, memory consumption is reduced to 1/3 of the original algorithm. Moreover, with the increasing of BUs, not only does throughput increase linearly, system latency also decreases linearly. This array processing orientated architecture provides flexible tradeoff between hardware cost and system performance. An 18-bit word-length 1024-point FFT architecture with 4 BUs is given to demonstrate this mapping algorithm. The design is implemented with TSMC 0.18μm CMOS technology. The core area is 2.99×1.12mm^{2} and clock frequency is 326MHz in typical condition (1.8V, 25°C). This processor could complete 1024 FFT calculation in 7.839μs.

Original language | English |
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Title of host publication | Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI |

Pages | 291-295 |

Number of pages | 5 |

Publication status | Published - 2005 |

Event | 2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 - Chicago, IL Duration: 2005 Apr 17 → 2005 Apr 19 |

### Other

Other | 2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 |
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City | Chicago, IL |

Period | 05/4/17 → 05/4/19 |

### Fingerprint

### Keywords

- Array Processing
- Fast Fourier Transform (FFT)
- Singleton Algorithm

### ASJC Scopus subject areas

- Engineering(all)

### Cite this

*Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI*(pp. 291-295). [S8.5S]

**A VLSI array processing oriented Fast Fourier Transform algorithm and hardware implementation.** / Liu, Zhenyu; Song, Yang; Ikenaga, Takeshi; Goto, Satoshi.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

*Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI.*, S8.5S, pp. 291-295, 2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05, Chicago, IL, 05/4/17.

}

TY - GEN

T1 - A VLSI array processing oriented Fast Fourier Transform algorithm and hardware implementation

AU - Liu, Zhenyu

AU - Song, Yang

AU - Ikenaga, Takeshi

AU - Goto, Satoshi

PY - 2005

Y1 - 2005

N2 - Many parallel Fast Fourier Transform (FFT) algorithms adopt multiple stages architecture to increase performance. However, data permutation between stages consumes volume memory and processing time. An FFT array processing mapping algorithm is proposed in this paper to overcome this demerit. In this algorithm, arbitrary 2k butterfly units (BUs) could be scheduled to work in parallel on n=2sdata (k=0, 1, ..., s-1). Because no inter stage data transfer is required, memory consumption is reduced to 1/3 of the original algorithm. Moreover, with the increasing of BUs, not only does throughput increase linearly, system latency also decreases linearly. This array processing orientated architecture provides flexible tradeoff between hardware cost and system performance. An 18-bit word-length 1024-point FFT architecture with 4 BUs is given to demonstrate this mapping algorithm. The design is implemented with TSMC 0.18μm CMOS technology. The core area is 2.99×1.12mm2 and clock frequency is 326MHz in typical condition (1.8V, 25°C). This processor could complete 1024 FFT calculation in 7.839μs.

AB - Many parallel Fast Fourier Transform (FFT) algorithms adopt multiple stages architecture to increase performance. However, data permutation between stages consumes volume memory and processing time. An FFT array processing mapping algorithm is proposed in this paper to overcome this demerit. In this algorithm, arbitrary 2k butterfly units (BUs) could be scheduled to work in parallel on n=2sdata (k=0, 1, ..., s-1). Because no inter stage data transfer is required, memory consumption is reduced to 1/3 of the original algorithm. Moreover, with the increasing of BUs, not only does throughput increase linearly, system latency also decreases linearly. This array processing orientated architecture provides flexible tradeoff between hardware cost and system performance. An 18-bit word-length 1024-point FFT architecture with 4 BUs is given to demonstrate this mapping algorithm. The design is implemented with TSMC 0.18μm CMOS technology. The core area is 2.99×1.12mm2 and clock frequency is 326MHz in typical condition (1.8V, 25°C). This processor could complete 1024 FFT calculation in 7.839μs.

KW - Array Processing

KW - Fast Fourier Transform (FFT)

KW - Singleton Algorithm

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M3 - Conference contribution

SP - 291

EP - 295

BT - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

ER -