A wide lock-in range PLL using self-calibrating technique for processors

Jingo Nakanishi, Hiromi Notani, Hiroshi Makino, Hirofumi Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A wide lock-in range PLL using a self-calibrating technique is proposed. This technique realizes a wide lock-in range and good jitter characteristics by performing the digital calibration at the start of the operation. However, self-calibration with a large number of digital control steps increases the test costs and circuit scale. In this paper, by estimating the margin for self-calibrating operation, the minimum number of digital control steps was determined. A PLL with a low test cost, a wide lock-in range and low jitter was designed and implemented using a 0.15 μm 1.5 V CMOS process. The measured PLL lock-in range is 80 MHz - 630 MHz with four digital calibration steps. The peak-to-peak jitter at 380 MHz is 100 ps.

Original languageEnglish
Title of host publication2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
Pages285-288
Number of pages4
DOIs
Publication statusPublished - 2006
Externally publishedYes
Event1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005 - Hsinchu, Taiwan, Province of China
Duration: 2005 Nov 12005 Nov 3

Other

Other1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005
CountryTaiwan, Province of China
CityHsinchu
Period05/11/105/11/3

Fingerprint

Phase locked loops
Jitter
Calibration
Costs
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Nakanishi, J., Notani, H., Makino, H., & Shinohara, H. (2006). A wide lock-in range PLL using self-calibrating technique for processors. In 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005 (pp. 285-288). [4017587] https://doi.org/10.1109/ASSCC.2005.251721

A wide lock-in range PLL using self-calibrating technique for processors. / Nakanishi, Jingo; Notani, Hiromi; Makino, Hiroshi; Shinohara, Hirofumi.

2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005. 2006. p. 285-288 4017587.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nakanishi, J, Notani, H, Makino, H & Shinohara, H 2006, A wide lock-in range PLL using self-calibrating technique for processors. in 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005., 4017587, pp. 285-288, 1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005, Hsinchu, Taiwan, Province of China, 05/11/1. https://doi.org/10.1109/ASSCC.2005.251721
Nakanishi J, Notani H, Makino H, Shinohara H. A wide lock-in range PLL using self-calibrating technique for processors. In 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005. 2006. p. 285-288. 4017587 https://doi.org/10.1109/ASSCC.2005.251721
Nakanishi, Jingo ; Notani, Hiromi ; Makino, Hiroshi ; Shinohara, Hirofumi. / A wide lock-in range PLL using self-calibrating technique for processors. 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005. 2006. pp. 285-288
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