A wide lock-in range PLL using self-calibrating technique for processors

Jingo Nakanishi, Hiromi Notani, Hiroshi Makino, Hirofumi Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A wide lock-in range PLL using a self-calibrating technique is proposed. This technique realizes a wide lock-in range and good jitter characteristics by performing the digital calibration at the start of the operation. However, self-calibration with a large number of digital control steps increases the test costs and circuit scale. In this paper, by estimating the margin for self-calibrating operation, the minimum number of digital control steps was determined. A PLL with a low test cost, a wide lock-in range and low jitter was designed and implemented using a 0.15 μm 1.5 V CMOS process. The measured PLL lock-in range is 80 MHz - 630 MHz with four digital calibration steps. The peak-to-peak jitter at 380 MHz is 100 ps.

Original languageEnglish
Title of host publication2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
PublisherIEEE Computer Society
Pages285-288
Number of pages4
ISBN (Print)0780391624, 9780780391628
DOIs
Publication statusPublished - 2005 Jan 1
Externally publishedYes
Event1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005 - Hsinchu, Taiwan, Province of China
Duration: 2005 Nov 12005 Nov 3

Publication series

Name2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Other

Other1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005
CountryTaiwan, Province of China
CityHsinchu
Period05/11/105/11/3

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Fingerprint Dive into the research topics of 'A wide lock-in range PLL using self-calibrating technique for processors'. Together they form a unique fingerprint.

  • Cite this

    Nakanishi, J., Notani, H., Makino, H., & Shinohara, H. (2005). A wide lock-in range PLL using self-calibrating technique for processors. In 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005 (pp. 285-288). [4017587] (2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005). IEEE Computer Society. https://doi.org/10.1109/ASSCC.2005.251721