Accelerating Multicore Architecture Simulation Using Application Profile

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    Architecture simulators play an important role in exploring frontiers in the early stages of the architecture design. However, the execution time of simulators increases with an increase the number of cores. The sampling simulation technique that was originally proposed to simulate single-core processors is a promising approach to reduce simulation time. Two main hurdles for multi/many-core are preparing sampling points and thread skewing at functional simulation time. This paper proposes a very simple and low-error sampling-based acceleration technique for multi/many-core simulators. For a parallelized application, an iteration of a large loop including a parallelizable program part, is defined as a sampling unit. We apply X-means method to a profile result of the collection of iterations derived from a real machine to form clusters of those iterations. Multiple iterations are exploited as sampling points from these clusters. We execute the simulation along the sampling points and calculate the number of total execution cycles. Results from a 16-core simulation show that our proposed simulation technique gives us a maximum of 443x speedup with a 0.52% error and 218x speedup with 1.50% error on an average.

    Original languageEnglish
    Title of host publicationProceedings - IEEE 10th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages177-184
    Number of pages8
    ISBN (Electronic)9781509035304
    DOIs
    Publication statusPublished - 2016 Dec 5
    Event10th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016 - Lyon, France
    Duration: 2016 Sep 212016 Sep 23

    Other

    Other10th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016
    CountryFrance
    CityLyon
    Period16/9/2116/9/23

    Fingerprint

    Sampling
    Simulators

    Keywords

    • Compiler
    • Multi/Many-core
    • Simulator

    ASJC Scopus subject areas

    • Computer Networks and Communications
    • Hardware and Architecture

    Cite this

    Kimura, K., Taguchi, G., & Kasahara, H. (2016). Accelerating Multicore Architecture Simulation Using Application Profile. In Proceedings - IEEE 10th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016 (pp. 177-184). [7774436] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MCSoC.2016.16

    Accelerating Multicore Architecture Simulation Using Application Profile. / Kimura, Keiji; Taguchi, Gakuho; Kasahara, Hironori.

    Proceedings - IEEE 10th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 177-184 7774436.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Kimura, K, Taguchi, G & Kasahara, H 2016, Accelerating Multicore Architecture Simulation Using Application Profile. in Proceedings - IEEE 10th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016., 7774436, Institute of Electrical and Electronics Engineers Inc., pp. 177-184, 10th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016, Lyon, France, 16/9/21. https://doi.org/10.1109/MCSoC.2016.16
    Kimura K, Taguchi G, Kasahara H. Accelerating Multicore Architecture Simulation Using Application Profile. In Proceedings - IEEE 10th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 177-184. 7774436 https://doi.org/10.1109/MCSoC.2016.16
    Kimura, Keiji ; Taguchi, Gakuho ; Kasahara, Hironori. / Accelerating Multicore Architecture Simulation Using Application Profile. Proceedings - IEEE 10th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 177-184
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