In this paper, to propose a model for access time analysis to achieve a high-speed access time, a signal path which determines the access time of dynamic MOS RAM has been analyzed and the technical issues necessary for high speed are examined. Further, based on the analysis of basic clock delay times and the sensing time, an access time analysis model is proposed. Using this model the sensitivity analysis for high-speed dynamic MOS RAM is performed, and the guidelines are given to realize high-speed dynamic MOS RAM.
|Number of pages||10|
|Journal||Electronics & communications in Japan|
|Publication status||Published - 1983 May|
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