Accurate method for calculating the effective capacitance with rc loads based on the thevenin model

Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Shuai Fang, Yasuaki Inoue

    Research output: Contribution to journalArticle

    2 Citations (Scopus)


    In deep submicron designs, predicting gate delays with interconnect load is a noteworthy work for Static Timing Analysis (STA). The effective capacitance Ceff concept and the Thevenin model that replaces the gate with a linear resistor and a voltage source are usually used to calculate the delay of gate with interconnect load. In conventional methods, it is not considered that the charges transferred into interconnect load and Ceff in the Thevenin model are not equal. The charge difference between interconnect load and Ceff has the large influence to the accuracy of computing C eff. In this paper, an advanced effective capacitance model is proposed to consider the above problem in the Thevenin model, where the influence of the charge difference is modeled as one part of the effective capacitance to compute the gate delay. Experimental results show a significant improvement in accuracy when the charge difference between interconnect load and Ceff is considered.

    Original languageEnglish
    Pages (from-to)2531-2539
    Number of pages9
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    Issue number10
    Publication statusPublished - 2009 Oct



    • Effective capacitance
    • Gate delay
    • Static timing analysis
    • Thevenin model

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Graphics and Computer-Aided Design
    • Applied Mathematics
    • Signal Processing

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