Adaptive error- and traffic-aware router architecture for 3D network-on-chip systems

Akram Ben Ahmed, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The advent of deep sub-micron and 3D integration technologies has exacerbated reliability issues in packet-switched on-chip interconnection networks. A lot of researches have been conducted in order to make these systems immune to any short-term malfunction or permanent physical damage while minimizing the performance degradation as much as possible. In this paper, we present an adaptive Error-, and Traffic-aware 3D-NoC router architecture, called 3D-Fault-Tolerant-OASIS (3D-FTO). 3D-FTO manages to avoid the system failure at the presence of a large number of faults and addresses the fault occurrence in links, input-buffers, and the crossbar, where the faults are more often to happen. The proposed 3D-FTO system was synthesized using Synopsis Design Compiler at 45nm CMOS process technology. Evaluation results show that our 3D-FTO is able to work around different kinds of faults ensuring graceful performance degradation while minimizing the additional hardware complexity and remaining power-efficient.

Original languageEnglish
Title of host publicationProceedings - 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages197-204
Number of pages8
ISBN (Electronic)9781479943050
DOIs
Publication statusPublished - 2014 Nov 6
Event2014 8th IEEE International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014 - Aizu-Wakamatsu, Japan
Duration: 2014 Sep 232014 Sep 25

Publication series

NameProceedings - 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014

Other

Other2014 8th IEEE International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014
CountryJapan
CityAizu-Wakamatsu
Period14/9/2314/9/25

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Keywords

  • 3D NoC
  • Adaptive
  • Error-aware
  • Traffic-aware

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Ahmed, A. B., Meyer, M., Okuyama, Y., & Abdallah, A. B. (2014). Adaptive error- and traffic-aware router architecture for 3D network-on-chip systems. In Proceedings - 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014 (pp. 197-204). [6949472] (Proceedings - 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MCSoC.2014.36