An 18.5ns 128Mb SOI DRAM with a floating body cell

Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Tomoki Higashi, Mutsuo Morikado, Yoshihiro Minami, Tomoaki Shino, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe

Research output: Contribution to journalConference article

1 Citation (Scopus)

Abstract

A dynamic latch sense amplifier/bit line replenishes "1" cells with holes lost during word line cycles and reduces the refresh busy rate. A multi-averaging method of dummy cells over 128 pairs of "1s" and "0s" enhances the sense margin and contributes to the 18.5ns access time. The 25.7ns virtually static RAM (VSRAM) mode is realized by taking advantage of the cell's quasi non-destructive read-out.

Original languageEnglish
Article number25.1
Pages (from-to)376-377+694
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume48
Publication statusPublished - 2005 Dec 6
Event2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: 2005 Feb 62005 Feb 10

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Ohsawa, T., Fujita, K., Hatsuda, K., Higashi, T., Morikado, M., Minami, Y., Shino, T., Nakajima, H., Inoh, K., Hamamoto, T., & Watanabe, S. (2005). An 18.5ns 128Mb SOI DRAM with a floating body cell. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 48, 376-377+694. [25.1].