An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller

Koichi Seki; Hitoshi Kume; Yuzuru Ohji; Takashi Kobayashi; Atsushi Hiraiwa; Takashi Nishida; Takeshi Wada; Kazuhiro Komori; Kazuto Izawa; Toshiaki Nishimoto; Yasuroh Kubota; Kazuyoshi Shohji

doi:10.1109/4.62136

An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller

Koichi Seki^*, Hitoshi Kume, Yuzuru Ohji, Takashi Kobayashi, Atsushi Hiraiwa, Takashi Nishida, Takeshi Wada, Kazuhiro Komori, Kazuto Izawa, Toshiaki Nishimoto, Yasuroh Kubota, Kazuyoshi Shohji

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

7 Citations (Scopus)

Abstract

An internal erase and erase-verify control system has been implemented in an electrically erasable, reprogrammable, 80-ns 1-Mb flash memory, which is suitable for in-system reprogram applications. The memory utilizes a one-transistor type cell with a cell area of 10.4 μ². The die area is 32.3 mm². An erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers as well as low-resistance polysilicide word lines and scaled periphery transistors. To realize high-sensitivity, high-speed sense circuits, a pMOS transistor (whose gate is connected to its drain) is used as a load transistor.

Original language	English
Pages (from-to)	1147-1152
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	25
Issue number	5
DOIs	https://doi.org/10.1109/4.62136
Publication status	Published - 1990 Oct
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/4.62136

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title = "An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller",

abstract = "An internal erase and erase-verify control system has been implemented in an electrically erasable, reprogrammable, 80-ns 1-Mb flash memory, which is suitable for in-system reprogram applications. The memory utilizes a one-transistor type cell with a cell area of 10.4 μ2. The die area is 32.3 mm2. An erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers as well as low-resistance polysilicide word lines and scaled periphery transistors. To realize high-sensitivity, high-speed sense circuits, a pMOS transistor (whose gate is connected to its drain) is used as a load transistor.",

author = "Koichi Seki and Hitoshi Kume and Yuzuru Ohji and Takashi Kobayashi and Atsushi Hiraiwa and Takashi Nishida and Takeshi Wada and Kazuhiro Komori and Kazuto Izawa and Toshiaki Nishimoto and Yasuroh Kubota and Kazuyoshi Shohji",

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AU - Seki, Koichi

AU - Kume, Hitoshi

AU - Ohji, Yuzuru

AU - Kobayashi, Takashi

AU - Hiraiwa, Atsushi

AU - Nishida, Takashi

AU - Wada, Takeshi

AU - Komori, Kazuhiro

AU - Izawa, Kazuto

AU - Nishimoto, Toshiaki

AU - Kubota, Yasuroh

AU - Shohji, Kazuyoshi

PY - 1990/10

Y1 - 1990/10

N2 - An internal erase and erase-verify control system has been implemented in an electrically erasable, reprogrammable, 80-ns 1-Mb flash memory, which is suitable for in-system reprogram applications. The memory utilizes a one-transistor type cell with a cell area of 10.4 μ2. The die area is 32.3 mm2. An erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers as well as low-resistance polysilicide word lines and scaled periphery transistors. To realize high-sensitivity, high-speed sense circuits, a pMOS transistor (whose gate is connected to its drain) is used as a load transistor.

AB - An internal erase and erase-verify control system has been implemented in an electrically erasable, reprogrammable, 80-ns 1-Mb flash memory, which is suitable for in-system reprogram applications. The memory utilizes a one-transistor type cell with a cell area of 10.4 μ2. The die area is 32.3 mm2. An erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers as well as low-resistance polysilicide word lines and scaled periphery transistors. To realize high-sensitivity, high-speed sense circuits, a pMOS transistor (whose gate is connected to its drain) is used as a load transistor.

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An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller

Abstract

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