An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller

Koichi Seki, Hitoshi Kume, Yuzuru Ohji, Takashi Kobayashi, Atsushi Hiraiwa, Takashi Nishida, Takeshi Wada, Kazuhiro Komori, Kazuto Izawa, Toshiaki Nishimoto, Yasuroh Kubota, Kazuyoshi Shohji

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

An internal erase and erase-verify control system has been implemented in an electrically erasable, reprogrammable, 80-ns 1-Mb flash memory, which is suitable for in-system reprogram applications. The memory utilizes a one-transistor type cell with a cell area of 10.4 μ2. The die area is 32.3 mm2. An erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers as well as low-resistance polysilicide word lines and scaled periphery transistors. To realize high-sensitivity, high-speed sense circuits, a pMOS transistor (whose gate is connected to its drain) is used as a load transistor.

Original languageEnglish
Pages (from-to)1147-1152
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume25
Issue number5
DOIs
Publication statusPublished - 1990 Oct
Externally publishedYes

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Flash memory
Transistors
Controllers
Control systems
Data storage equipment
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Seki, K., Kume, H., Ohji, Y., Kobayashi, T., Hiraiwa, A., Nishida, T., ... Shohji, K. (1990). An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller. IEEE Journal of Solid-State Circuits, 25(5), 1147-1152. https://doi.org/10.1109/4.62136

An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller. / Seki, Koichi; Kume, Hitoshi; Ohji, Yuzuru; Kobayashi, Takashi; Hiraiwa, Atsushi; Nishida, Takashi; Wada, Takeshi; Komori, Kazuhiro; Izawa, Kazuto; Nishimoto, Toshiaki; Kubota, Yasuroh; Shohji, Kazuyoshi.

In: IEEE Journal of Solid-State Circuits, Vol. 25, No. 5, 10.1990, p. 1147-1152.

Research output: Contribution to journalArticle

Seki, K, Kume, H, Ohji, Y, Kobayashi, T, Hiraiwa, A, Nishida, T, Wada, T, Komori, K, Izawa, K, Nishimoto, T, Kubota, Y & Shohji, K 1990, 'An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller', IEEE Journal of Solid-State Circuits, vol. 25, no. 5, pp. 1147-1152. https://doi.org/10.1109/4.62136
Seki K, Kume H, Ohji Y, Kobayashi T, Hiraiwa A, Nishida T et al. An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller. IEEE Journal of Solid-State Circuits. 1990 Oct;25(5):1147-1152. https://doi.org/10.1109/4.62136
Seki, Koichi ; Kume, Hitoshi ; Ohji, Yuzuru ; Kobayashi, Takashi ; Hiraiwa, Atsushi ; Nishida, Takashi ; Wada, Takeshi ; Komori, Kazuhiro ; Izawa, Kazuto ; Nishimoto, Toshiaki ; Kubota, Yasuroh ; Shohji, Kazuyoshi. / An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller. In: IEEE Journal of Solid-State Circuits. 1990 ; Vol. 25, No. 5. pp. 1147-1152.
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