An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller

Koichi Seki, Hitoshi Kume, Yuzuru Ohji, Takashi Kobayashi, Atsushi Hiraiwa, Takashi Nishida, Takeshi Wada, Kazuhiro Komori, Kazuto Izawa, Toshiaki Nishimoto, Yasuroh Kubota, Kazuyoshi Shohji

Research output: Contribution to journalArticle

7 Citations (Scopus)


An internal erase and erase-verify control system has been implemented in an electrically erasable, reprogrammable, 80-ns 1-Mb flash memory, which is suitable for in-system reprogram applications. The memory utilizes a one-transistor type cell with a cell area of 10.4 μ2. The die area is 32.3 mm2. An erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers as well as low-resistance polysilicide word lines and scaled periphery transistors. To realize high-sensitivity, high-speed sense circuits, a pMOS transistor (whose gate is connected to its drain) is used as a load transistor.

Original languageEnglish
Pages (from-to)1147-1152
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Issue number5
Publication statusPublished - 1990 Oct
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Seki, K., Kume, H., Ohji, Y., Kobayashi, T., Hiraiwa, A., Nishida, T., Wada, T., Komori, K., Izawa, K., Nishimoto, T., Kubota, Y., & Shohji, K. (1990). An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller. IEEE Journal of Solid-State Circuits, 25(5), 1147-1152.