An 8640 MIPS SoC with independent power-off control of 8 CPUs and 8 RAMs by an automatic parallelizing compiler

Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Masaki Ito, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

34 Citations (Scopus)

Abstract

A 104.8mm2 90nm CMOS 600MHz SoC integrates 8 processor cores and 8 user RAMs in 17 separate power domains and delivers 33.6GFLOPS. An automatic parallelizing compiler assigns tasks to each CPU and controls its power mode including power supply in accordance with its processing load and status. The compiler also uses barrier registers to achieve fast and accurate CPU synchronization.

Original languageEnglish
Title of host publication2008 IEEE International Solid State Circuits Conference - Digest of Technical Papers, ISSCC
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages89-91
Number of pages3
ISBN (Print)9781424420100
DOIs
Publication statusPublished - 2008
Event2008 IEEE International Solid State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: 2008 Feb 32008 Feb 7

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume51
ISSN (Print)0193-6530

Conference

Conference2008 IEEE International Solid State Circuits Conference, ISSCC
CountryUnited States
CitySan Francisco, CA
Period08/2/308/2/7

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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