An 8.8-ns 54 × 54-bit multiplier with high speed redundant binary architecture

Hiroshi Makino*, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

108 Citations (Scopus)

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Engineering & Materials Science