An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design

Dajiang Zhou, Shihao Wang, Heming Sun, Jianbin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

8K ultra-HD is being promoted as the next-generation video specification. While the High Efficiency Video Coding (HEVC) standard greatly enhances the feasibility of 8K with a doubled compression ratio, its implementation is a challenge, owing to ultrahigh-throughput requirements and increased complexity per pixel. The latter comes from the new features of HEVC. At the system level, the most challenging of them is the enlarged and highly variable-size coding/prediction/transform units, which significantly increase the requirement for on-chip memory as pipeline buffers and the difficulty in maintaining pipeline utilization. This paper presents an HEVC decoder chip featuring a system pipeline that works at a nonunified and variable granularity. The pipeline saves on-chip memory with a novel block-in-block-out queue system and a parameter delivery network, while allowing overhead-free and fully pipelined operation of the processing components. With the system pipeline design combined with various component-level optimizations, the proposed decoder in 40 nm achieves a maximum throughput of 4 Gpixels/s or 8K 120 frames/s for the low-delay-P configuration of HEVC, 7.5-55 times faster than prior works. It supports 8K 60 frames/s for the low-delay and random-access configurations. In a normalized comparison, it also shows 3.1-3.6 times better area efficiency and 31%-55% superior energy efficiency.

Original languageEnglish
JournalIEEE Journal of Solid-State Circuits
DOIs
Publication statusAccepted/In press - 2016 Nov 4

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Image coding
Pipelines
Throughput
Data storage equipment
Energy efficiency
Pixels
Mathematical transformations
Specifications
Processing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design. / Zhou, Dajiang; Wang, Shihao; Sun, Heming; Zhou, Jianbin; Zhu, Jiayi; Zhao, Yijin; Zhou, Jinjia; Zhang, Shuping; Kimura, Shinji; Yoshimura, Takeshi; Goto, Satoshi.

In: IEEE Journal of Solid-State Circuits, 04.11.2016.

Research output: Contribution to journalArticle

Zhou, Dajiang ; Wang, Shihao ; Sun, Heming ; Zhou, Jianbin ; Zhu, Jiayi ; Zhao, Yijin ; Zhou, Jinjia ; Zhang, Shuping ; Kimura, Shinji ; Yoshimura, Takeshi ; Goto, Satoshi. / An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design. In: IEEE Journal of Solid-State Circuits. 2016.
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