An adaptive test for parametric faults based on statistical timing information

Michihiro Shintani; Takumi Uezono; Tomoyuki Takahashi; Hiroyuki Ueyama; Takashi Sato; Kazumi Hatayama; Takashi Aikyo; Kazuya Masu

doi:10.1109/ATS.2009.90

An adaptive test for parametric faults based on statistical timing information

Michihiro Shintani^*, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Citations (Scopus)

Abstract

The continuing miniaturization of LSI dimension is causing the increase of process-Related variations which significantly affects not only its design turn around time but also its manufacturing yield. Statistical static timing analysis (SSTA) is expected as a promising way to estimate the performance of circuits more accurately considering delay variations. However, LSIs designed using SSTA may have higher probability of parametric faults than the ones designed with deterministic timing analysis. In order to test these parametric faults, effective extraction techniques of critical paths are needed. In this paper, we discuss a general trend between the delay margin of LSIs designed by SSTA and their parametric fault ratio. Then we propose an adaptive test flow for parametric faults using statistical static timing information, and a concept of parametric fault coverage. Experimental results demonstrate the effectiveness of our approach.

Original language	English
Title of host publication	Proceedings of the 18th Asian Test Symposium, ATS 2009
Pages	151-156
Number of pages	6
DOIs	https://doi.org/10.1109/ATS.2009.90
Publication status	Published - 2009
Externally published	Yes
Event	18th Asian Test Symposium, ATS 2009 - Taichung, Taiwan, Province of China Duration: 2009 Nov 23 → 2009 Nov 26

Publication series

Name	Proceedings of the Asian Test Symposium
ISSN (Print)	1081-7735

Conference

Conference	18th Asian Test Symposium, ATS 2009
Country/Territory	Taiwan, Province of China
City	Taichung
Period	09/11/23 → 09/11/26

Keywords

Parametric fault
Path-delay test
SSTA

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ATS.2009.90

Cite this

Shintani, M, Uezono, T, Takahashi, T, Ueyama, H, Sato, T, Hatayama, K, Aikyo, T & Masu, K 2009, An adaptive test for parametric faults based on statistical timing information. in Proceedings of the 18th Asian Test Symposium, ATS 2009., 5359374, Proceedings of the Asian Test Symposium, pp. 151-156, 18th Asian Test Symposium, ATS 2009, Taichung, Taiwan, Province of China, 09/11/23. https://doi.org/10.1109/ATS.2009.90

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title = "An adaptive test for parametric faults based on statistical timing information",

abstract = "The continuing miniaturization of LSI dimension is causing the increase of process-Related variations which significantly affects not only its design turn around time but also its manufacturing yield. Statistical static timing analysis (SSTA) is expected as a promising way to estimate the performance of circuits more accurately considering delay variations. However, LSIs designed using SSTA may have higher probability of parametric faults than the ones designed with deterministic timing analysis. In order to test these parametric faults, effective extraction techniques of critical paths are needed. In this paper, we discuss a general trend between the delay margin of LSIs designed by SSTA and their parametric fault ratio. Then we propose an adaptive test flow for parametric faults using statistical static timing information, and a concept of parametric fault coverage. Experimental results demonstrate the effectiveness of our approach.",

keywords = "Parametric fault, Path-delay test, SSTA",

author = "Michihiro Shintani and Takumi Uezono and Tomoyuki Takahashi and Hiroyuki Ueyama and Takashi Sato and Kazumi Hatayama and Takashi Aikyo and Kazuya Masu",

year = "2009",

doi = "10.1109/ATS.2009.90",

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T1 - An adaptive test for parametric faults based on statistical timing information

AU - Shintani, Michihiro

AU - Uezono, Takumi

AU - Takahashi, Tomoyuki

AU - Ueyama, Hiroyuki

AU - Sato, Takashi

AU - Hatayama, Kazumi

AU - Aikyo, Takashi

AU - Masu, Kazuya

PY - 2009

Y1 - 2009

N2 - The continuing miniaturization of LSI dimension is causing the increase of process-Related variations which significantly affects not only its design turn around time but also its manufacturing yield. Statistical static timing analysis (SSTA) is expected as a promising way to estimate the performance of circuits more accurately considering delay variations. However, LSIs designed using SSTA may have higher probability of parametric faults than the ones designed with deterministic timing analysis. In order to test these parametric faults, effective extraction techniques of critical paths are needed. In this paper, we discuss a general trend between the delay margin of LSIs designed by SSTA and their parametric fault ratio. Then we propose an adaptive test flow for parametric faults using statistical static timing information, and a concept of parametric fault coverage. Experimental results demonstrate the effectiveness of our approach.

AB - The continuing miniaturization of LSI dimension is causing the increase of process-Related variations which significantly affects not only its design turn around time but also its manufacturing yield. Statistical static timing analysis (SSTA) is expected as a promising way to estimate the performance of circuits more accurately considering delay variations. However, LSIs designed using SSTA may have higher probability of parametric faults than the ones designed with deterministic timing analysis. In order to test these parametric faults, effective extraction techniques of critical paths are needed. In this paper, we discuss a general trend between the delay margin of LSIs designed by SSTA and their parametric fault ratio. Then we propose an adaptive test flow for parametric faults using statistical static timing information, and a concept of parametric fault coverage. Experimental results demonstrate the effectiveness of our approach.

KW - Parametric fault

KW - Path-delay test

KW - SSTA

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Y2 - 23 November 2009 through 26 November 2009

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An adaptive test for parametric faults based on statistical timing information

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

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