An adaptive test for parametric faults based on statistical timing information

Michihiro Shintani*, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)


The continuing miniaturization of LSI dimension is causing the increase of process-Related variations which significantly affects not only its design turn around time but also its manufacturing yield. Statistical static timing analysis (SSTA) is expected as a promising way to estimate the performance of circuits more accurately considering delay variations. However, LSIs designed using SSTA may have higher probability of parametric faults than the ones designed with deterministic timing analysis. In order to test these parametric faults, effective extraction techniques of critical paths are needed. In this paper, we discuss a general trend between the delay margin of LSIs designed by SSTA and their parametric fault ratio. Then we propose an adaptive test flow for parametric faults using statistical static timing information, and a concept of parametric fault coverage. Experimental results demonstrate the effectiveness of our approach.

Original languageEnglish
Title of host publicationProceedings of the 18th Asian Test Symposium, ATS 2009
Number of pages6
Publication statusPublished - 2009
Externally publishedYes
Event18th Asian Test Symposium, ATS 2009 - Taichung, Taiwan, Province of China
Duration: 2009 Nov 232009 Nov 26

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735


Conference18th Asian Test Symposium, ATS 2009
Country/TerritoryTaiwan, Province of China


  • Parametric fault
  • Path-delay test
  • SSTA

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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