The continuing miniaturization of LSI dimension is causing the increase of process-Related variations which significantly affects not only its design turn around time but also its manufacturing yield. Statistical static timing analysis (SSTA) is expected as a promising way to estimate the performance of circuits more accurately considering delay variations. However, LSIs designed using SSTA may have higher probability of parametric faults than the ones designed with deterministic timing analysis. In order to test these parametric faults, effective extraction techniques of critical paths are needed. In this paper, we discuss a general trend between the delay margin of LSIs designed by SSTA and their parametric fault ratio. Then we propose an adaptive test flow for parametric faults using statistical static timing information, and a concept of parametric fault coverage. Experimental results demonstrate the effectiveness of our approach.