An adaptive width data cache for low power design

Jiongyao Ye, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

Reducing the power consumption is one of the most important design problems at present. Modern microprocessors employ caches to bridge the great speed variance between the main memory and the central processing unit, but these caches propose larger and larger proportion in the total power consumption. The Narrow-Width Value (NWV) occupies a large portion of cache access and storage. The storage space for value of any data width is the same in the cache, even if NWV needs only a few bits to be stored. This paper proposes an Adaptive Width Data Cache (AWDC) which exploits the popularity of NWV stored in the cache. In AWDC, the cache data array is divided into several data arrays to adapt different data width to access/store. Its purpose is shutting off corresponding unused high arrays to reduce its dynamic and static power consumption. AWDC achieves low power consumption only by the modification of the high-bit SRAM unit almost without any additional hardware, and does not affect cache performance. Experimental results employing SPEC 2000 benchmarks show that our proposed AWDC can reduce both the dynamic power consumption ant the static power consumption by 44.75% and 42.86%.

Original languageEnglish
Title of host publication2009 International SoC Design Conference, ISOCC 2009
Pages488-491
Number of pages4
DOIs
Publication statusPublished - 2009
Event2009 International SoC Design Conference, ISOCC 2009 - Busan
Duration: 2009 Nov 222009 Nov 24

Other

Other2009 International SoC Design Conference, ISOCC 2009
CityBusan
Period09/11/2209/11/24

Fingerprint

Electric power utilization
Static random access storage
Program processors
Microprocessor chips
Hardware
Data storage equipment

Keywords

  • Component
  • Data cache
  • Dynamic power
  • Low power
  • Nattow-width value
  • Static power

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Ye, J., & Watanabe, T. (2009). An adaptive width data cache for low power design. In 2009 International SoC Design Conference, ISOCC 2009 (pp. 488-491). [5423919] https://doi.org/10.1109/SOCDC.2009.5423919

An adaptive width data cache for low power design. / Ye, Jiongyao; Watanabe, Takahiro.

2009 International SoC Design Conference, ISOCC 2009. 2009. p. 488-491 5423919.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ye, J & Watanabe, T 2009, An adaptive width data cache for low power design. in 2009 International SoC Design Conference, ISOCC 2009., 5423919, pp. 488-491, 2009 International SoC Design Conference, ISOCC 2009, Busan, 09/11/22. https://doi.org/10.1109/SOCDC.2009.5423919
Ye J, Watanabe T. An adaptive width data cache for low power design. In 2009 International SoC Design Conference, ISOCC 2009. 2009. p. 488-491. 5423919 https://doi.org/10.1109/SOCDC.2009.5423919
Ye, Jiongyao ; Watanabe, Takahiro. / An adaptive width data cache for low power design. 2009 International SoC Design Conference, ISOCC 2009. 2009. pp. 488-491
@inproceedings{383304c6bdfa4e47ae6439e8bf05da91,
title = "An adaptive width data cache for low power design",
abstract = "Reducing the power consumption is one of the most important design problems at present. Modern microprocessors employ caches to bridge the great speed variance between the main memory and the central processing unit, but these caches propose larger and larger proportion in the total power consumption. The Narrow-Width Value (NWV) occupies a large portion of cache access and storage. The storage space for value of any data width is the same in the cache, even if NWV needs only a few bits to be stored. This paper proposes an Adaptive Width Data Cache (AWDC) which exploits the popularity of NWV stored in the cache. In AWDC, the cache data array is divided into several data arrays to adapt different data width to access/store. Its purpose is shutting off corresponding unused high arrays to reduce its dynamic and static power consumption. AWDC achieves low power consumption only by the modification of the high-bit SRAM unit almost without any additional hardware, and does not affect cache performance. Experimental results employing SPEC 2000 benchmarks show that our proposed AWDC can reduce both the dynamic power consumption ant the static power consumption by 44.75{\%} and 42.86{\%}.",
keywords = "Component, Data cache, Dynamic power, Low power, Nattow-width value, Static power",
author = "Jiongyao Ye and Takahiro Watanabe",
year = "2009",
doi = "10.1109/SOCDC.2009.5423919",
language = "English",
isbn = "9781424450343",
pages = "488--491",
booktitle = "2009 International SoC Design Conference, ISOCC 2009",

}

TY - GEN

T1 - An adaptive width data cache for low power design

AU - Ye, Jiongyao

AU - Watanabe, Takahiro

PY - 2009

Y1 - 2009

N2 - Reducing the power consumption is one of the most important design problems at present. Modern microprocessors employ caches to bridge the great speed variance between the main memory and the central processing unit, but these caches propose larger and larger proportion in the total power consumption. The Narrow-Width Value (NWV) occupies a large portion of cache access and storage. The storage space for value of any data width is the same in the cache, even if NWV needs only a few bits to be stored. This paper proposes an Adaptive Width Data Cache (AWDC) which exploits the popularity of NWV stored in the cache. In AWDC, the cache data array is divided into several data arrays to adapt different data width to access/store. Its purpose is shutting off corresponding unused high arrays to reduce its dynamic and static power consumption. AWDC achieves low power consumption only by the modification of the high-bit SRAM unit almost without any additional hardware, and does not affect cache performance. Experimental results employing SPEC 2000 benchmarks show that our proposed AWDC can reduce both the dynamic power consumption ant the static power consumption by 44.75% and 42.86%.

AB - Reducing the power consumption is one of the most important design problems at present. Modern microprocessors employ caches to bridge the great speed variance between the main memory and the central processing unit, but these caches propose larger and larger proportion in the total power consumption. The Narrow-Width Value (NWV) occupies a large portion of cache access and storage. The storage space for value of any data width is the same in the cache, even if NWV needs only a few bits to be stored. This paper proposes an Adaptive Width Data Cache (AWDC) which exploits the popularity of NWV stored in the cache. In AWDC, the cache data array is divided into several data arrays to adapt different data width to access/store. Its purpose is shutting off corresponding unused high arrays to reduce its dynamic and static power consumption. AWDC achieves low power consumption only by the modification of the high-bit SRAM unit almost without any additional hardware, and does not affect cache performance. Experimental results employing SPEC 2000 benchmarks show that our proposed AWDC can reduce both the dynamic power consumption ant the static power consumption by 44.75% and 42.86%.

KW - Component

KW - Data cache

KW - Dynamic power

KW - Low power

KW - Nattow-width value

KW - Static power

UR - http://www.scopus.com/inward/record.url?scp=77951468820&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77951468820&partnerID=8YFLogxK

U2 - 10.1109/SOCDC.2009.5423919

DO - 10.1109/SOCDC.2009.5423919

M3 - Conference contribution

AN - SCOPUS:77951468820

SN - 9781424450343

SP - 488

EP - 491

BT - 2009 International SoC Design Conference, ISOCC 2009

ER -