An adder-segmentation-based FIR for high speed signal processing

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An advanced adder-segmentation-based FIR filter design for high speed signal processing is proposed in this paper. In the proposed method, the critical path delay is shortened through adder segmentation. An analysis for the optimization of adder segmentation is also proposed, which can be used for critical path delay balance to maximize the performance of FIR filters. The evaluation results show that the proposed design can achieve up to 30.7% and 22.8% reduction in area-delay-product (ADP) and energy-delay-product (EDP) when compared with the existing FIR filters.

Original languageEnglish
Title of host publicationProceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019
EditorsFan Ye, Ting-Ao Tang
PublisherIEEE Computer Society
ISBN (Electronic)9781728107356
DOIs
Publication statusPublished - 2019 Oct
Event13th IEEE International Conference on ASIC, ASICON 2019 - Chongqing, China
Duration: 2019 Oct 292019 Nov 1

Publication series

NameProceedings of International Conference on ASIC
ISSN (Print)2162-7541
ISSN (Electronic)2162-755X

Conference

Conference13th IEEE International Conference on ASIC, ASICON 2019
CountryChina
CityChongqing
Period19/10/2919/11/1

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Ye, J., Yanagisawa, M., & Shi, Y. (2019). An adder-segmentation-based FIR for high speed signal processing. In F. Ye, & T-A. Tang (Eds.), Proceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019 [8983612] (Proceedings of International Conference on ASIC). IEEE Computer Society. https://doi.org/10.1109/ASICON47005.2019.8983612