An advanced effective capacitance model for calculating gate delay considering input waveform effect

Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Na Li, Yasuaki Inoue

    Research output: Contribution to journalArticle


    In deep submicron designs, predicting gate delay time is a noteworthy work for Static Timing Analysis. The effective capacitance Ceff concept is usually used to calculate the gate delay with interconnect loads. Conventionally, the input-signal to the gate is always assumed as a ramp waveform. However, the input signal is also the output of CMOS gates with interconnect loads and not the ramp waveform. Thus the simple assumption as a ramp signal results in significant influence on the delay calculation. In this paper, an advanced effective capacitance model is proposed to consider both the input waveform effect and the interconnect loads, where the nonlinear influence of input waveform is modeled as one part of the effective capacitance for calculating the gate delay. Experimental results show a significant improvement in accuracy when the input waveform effect is considered.

    Original languageEnglish
    Pages (from-to)633-639
    Number of pages7
    JournalChinese Journal of Electronics
    Issue number4
    Publication statusPublished - 2008 Oct



    • CMOS gate
    • Effective capacitance
    • Gate delay
    • Input waveform effect

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Applied Mathematics

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