An algorithm and a flexible architecture for fast block-matching motion estimation

Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Research output: Contribution to journalArticle

    3 Citations (Scopus)

    Abstract

    The motion estimation can choose the most suitable algorithm for different kinds of motion types, formats, and characteristics. The video encoding system can be optimized for quality, speed, and power consumption. In this paper, we propose a reconfigurable approach to a motion estimation algorithm and hardware architecture. The proposed algorithm determines motion type and then selects adapted block-matching algorithm for different kinds of motion sequences. The quality of our algorithm is better than that of the TSS and the BBGDS algorithm, or comparable to the performance of the better of the two, and the computational complexity of our algorithm is significantly less than that of the TSS. We also propose hardware architecture for realizing two kinds of motion estimations in the same hardware. We implemented the flexible and reconfigurable hardware architecture by using address generator unit, delay unit, and parameters and by using the hardware description language (VHDL) and the SYNOPSYS synthesis design tools. We analyze the performance of the algorithm and present adapted algorithm for a low cost real time application.

    Original languageEnglish
    Pages (from-to)2603-2611
    Number of pages9
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE85-A
    Issue number12
    Publication statusPublished - 2002 Dec

    Fingerprint

    Block Matching
    Motion Estimation
    Motion estimation
    Hardware Architecture
    Computer hardware description languages
    Motion
    Hardware
    Reconfigurable Architectures
    Reconfigurable Hardware
    Block Algorithm
    Unit
    Matching Algorithm
    Reconfigurable hardware
    Estimation Algorithms
    Architecture
    Power Consumption
    Computational Complexity
    Encoding
    Choose
    Computer hardware

    Keywords

    • Algorithm
    • Architecture
    • Block-matching
    • Motion estimation
    • VHDL

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Information Systems
    • Electrical and Electronic Engineering

    Cite this

    @article{185c0537462640a3a1092852f7b9596c,
    title = "An algorithm and a flexible architecture for fast block-matching motion estimation",
    abstract = "The motion estimation can choose the most suitable algorithm for different kinds of motion types, formats, and characteristics. The video encoding system can be optimized for quality, speed, and power consumption. In this paper, we propose a reconfigurable approach to a motion estimation algorithm and hardware architecture. The proposed algorithm determines motion type and then selects adapted block-matching algorithm for different kinds of motion sequences. The quality of our algorithm is better than that of the TSS and the BBGDS algorithm, or comparable to the performance of the better of the two, and the computational complexity of our algorithm is significantly less than that of the TSS. We also propose hardware architecture for realizing two kinds of motion estimations in the same hardware. We implemented the flexible and reconfigurable hardware architecture by using address generator unit, delay unit, and parameters and by using the hardware description language (VHDL) and the SYNOPSYS synthesis design tools. We analyze the performance of the algorithm and present adapted algorithm for a low cost real time application.",
    keywords = "Algorithm, Architecture, Block-matching, Motion estimation, VHDL",
    author = "Jinku Choi and Nozomu Togawa and Masao Yanagisawa and Tatsuo Ohtsuki",
    year = "2002",
    month = "12",
    language = "English",
    volume = "E85-A",
    pages = "2603--2611",
    journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
    issn = "0916-8508",
    publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
    number = "12",

    }

    TY - JOUR

    T1 - An algorithm and a flexible architecture for fast block-matching motion estimation

    AU - Choi, Jinku

    AU - Togawa, Nozomu

    AU - Yanagisawa, Masao

    AU - Ohtsuki, Tatsuo

    PY - 2002/12

    Y1 - 2002/12

    N2 - The motion estimation can choose the most suitable algorithm for different kinds of motion types, formats, and characteristics. The video encoding system can be optimized for quality, speed, and power consumption. In this paper, we propose a reconfigurable approach to a motion estimation algorithm and hardware architecture. The proposed algorithm determines motion type and then selects adapted block-matching algorithm for different kinds of motion sequences. The quality of our algorithm is better than that of the TSS and the BBGDS algorithm, or comparable to the performance of the better of the two, and the computational complexity of our algorithm is significantly less than that of the TSS. We also propose hardware architecture for realizing two kinds of motion estimations in the same hardware. We implemented the flexible and reconfigurable hardware architecture by using address generator unit, delay unit, and parameters and by using the hardware description language (VHDL) and the SYNOPSYS synthesis design tools. We analyze the performance of the algorithm and present adapted algorithm for a low cost real time application.

    AB - The motion estimation can choose the most suitable algorithm for different kinds of motion types, formats, and characteristics. The video encoding system can be optimized for quality, speed, and power consumption. In this paper, we propose a reconfigurable approach to a motion estimation algorithm and hardware architecture. The proposed algorithm determines motion type and then selects adapted block-matching algorithm for different kinds of motion sequences. The quality of our algorithm is better than that of the TSS and the BBGDS algorithm, or comparable to the performance of the better of the two, and the computational complexity of our algorithm is significantly less than that of the TSS. We also propose hardware architecture for realizing two kinds of motion estimations in the same hardware. We implemented the flexible and reconfigurable hardware architecture by using address generator unit, delay unit, and parameters and by using the hardware description language (VHDL) and the SYNOPSYS synthesis design tools. We analyze the performance of the algorithm and present adapted algorithm for a low cost real time application.

    KW - Algorithm

    KW - Architecture

    KW - Block-matching

    KW - Motion estimation

    KW - VHDL

    UR - http://www.scopus.com/inward/record.url?scp=0037004105&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=0037004105&partnerID=8YFLogxK

    M3 - Article

    AN - SCOPUS:0037004105

    VL - E85-A

    SP - 2603

    EP - 2611

    JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    SN - 0916-8508

    IS - 12

    ER -