An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions

Y. Miyaoka, J. Choi, Nozomu Togawa, Masao Yanagisawa, T. Ohtsuki

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    The authors consider the synthesis of a processor core with SIMD instructions by a hardware/software cosynthesis system. The system is required to configure functional units executing SIMD instructions and obtain the area and delay of the functional units to evaluate the synthesized processor core. This paper proposes a hardware unit generation algorithm for a hardware/software cosynthesis system of processors with SIMD instructions. Given a set of instructions to be executed by a hardware unit and constraints for area and delay of the hardware unit, the proposed algorithm extracts a set of subfunctions to be required by the hardware unit and generates more than one architecture candidates for the hardware unit. The algorithm also outputs the estimated area and delay of each of the generated hardware units. The execution time of the proposed algorithm is very short and thus it can be easily incorporated into the processor core synthesis system. Experimental results demonstrate effectiveness and efficiency of the algorithm.

    Original languageEnglish
    Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages171-176
    Number of pages6
    Volume1
    ISBN (Print)0780376900
    DOIs
    Publication statusPublished - 2002
    EventAsia-Pacific Conference on Circuits and Systems, APCCAS 2002 - Denpasar, Bali, Indonesia
    Duration: 2002 Oct 282002 Oct 31

    Other

    OtherAsia-Pacific Conference on Circuits and Systems, APCCAS 2002
    CountryIndonesia
    CityDenpasar, Bali
    Period02/10/2802/10/31

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    Hardware

    Keywords

    • Application software
    • Delay estimation
    • Digital signal processors
    • Hardware
    • Image processing
    • Pixel
    • Signal synthesis
    • Software algorithms
    • Software systems

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Miyaoka, Y., Choi, J., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2002). An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS (Vol. 1, pp. 171-176). [1114930] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2002.1114930

    An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. / Miyaoka, Y.; Choi, J.; Togawa, Nozomu; Yanagisawa, Masao; Ohtsuki, T.

    IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Vol. 1 Institute of Electrical and Electronics Engineers Inc., 2002. p. 171-176 1114930.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Miyaoka, Y, Choi, J, Togawa, N, Yanagisawa, M & Ohtsuki, T 2002, An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. in IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. vol. 1, 1114930, Institute of Electrical and Electronics Engineers Inc., pp. 171-176, Asia-Pacific Conference on Circuits and Systems, APCCAS 2002, Denpasar, Bali, Indonesia, 02/10/28. https://doi.org/10.1109/APCCAS.2002.1114930
    Miyaoka Y, Choi J, Togawa N, Yanagisawa M, Ohtsuki T. An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Vol. 1. Institute of Electrical and Electronics Engineers Inc. 2002. p. 171-176. 1114930 https://doi.org/10.1109/APCCAS.2002.1114930
    Miyaoka, Y. ; Choi, J. ; Togawa, Nozomu ; Yanagisawa, Masao ; Ohtsuki, T. / An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. Vol. 1 Institute of Electrical and Electronics Engineers Inc., 2002. pp. 171-176
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