@inproceedings{f0b4b361ab88429284f7d4ba4ce88984,
title = "An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions",
abstract = "The authors consider the synthesis of a processor core with SIMD instructions by a hardware/software cosynthesis system. The system is required to configure functional units executing SIMD instructions and obtain the area and delay of the functional units to evaluate the synthesized processor core. This paper proposes a hardware unit generation algorithm for a hardware/software cosynthesis system of processors with SIMD instructions. Given a set of instructions to be executed by a hardware unit and constraints for area and delay of the hardware unit, the proposed algorithm extracts a set of subfunctions to be required by the hardware unit and generates more than one architecture candidates for the hardware unit. The algorithm also outputs the estimated area and delay of each of the generated hardware units. The execution time of the proposed algorithm is very short and thus it can be easily incorporated into the processor core synthesis system. Experimental results demonstrate effectiveness and efficiency of the algorithm.",
keywords = "Application software, Delay estimation, Digital signal processors, Hardware, Image processing, Pixel, Signal synthesis, Software algorithms, Software systems",
author = "Y. Miyaoka and J. Choi and N. Togawa and M. Yanagisawa and T. Ohtsuki",
note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; Asia-Pacific Conference on Circuits and Systems, APCCAS 2002 ; Conference date: 28-10-2002 Through 31-10-2002",
year = "2002",
doi = "10.1109/APCCAS.2002.1114930",
language = "English",
series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "171--176",
booktitle = "Proceedings - APCCAS 2002",
}