An analytical model of the overshooting effect for multiple-input gates in nanometer technologies

Li Ding, Jing Wang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    The overshooting effect, which is induced by the input-to-output coupling capacitance, has an significant effect on CMOS gate delay with the scaling of CMOS technology. In this paper, an effective analytical model is proposed to calculate the overshooting time of multiple-input gates. The proposed model is verified having a good agreement with SPICE simulation results.

    Original languageEnglish
    Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
    Pages1712-1715
    Number of pages4
    DOIs
    Publication statusPublished - 2013
    Event2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing
    Duration: 2013 May 192013 May 23

    Other

    Other2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
    CityBeijing
    Period13/5/1913/5/23

      Fingerprint

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Ding, L., Wang, J., Huang, Z., Kurokawa, A., & Inoue, Y. (2013). An analytical model of the overshooting effect for multiple-input gates in nanometer technologies. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 1712-1715). [6572194] https://doi.org/10.1109/ISCAS.2013.6572194