An area-effective datapath architecture for embedded microprocessors and scalable systems

Toshiaki Inoue, Takashi Manabe, Sunao Torii, Satoshi Masushita, Masato Edahiro, Naoki Nishi, Masakazu Yamashina

Research output: Contribution to journalArticle

Abstract

We have proposed area-reduction techniques for superscalar datapath architectures with 34 SIMD instructions and have developed an integer-media unit based on these techniques. The unit's design is both functionally asymmetrical and integer-SIMD unified, and the resulting savings in area are 27%-48% as compared to other, functionally equivalent mid-level microprocessor designs, with performance that is, at most, only 7.2% lower. Further, in 2-D IDCT processing, the unit outperforms embedded microprocessor designs without SIMD functions by 49%-118%. Specifically, effective area reduction of adders, shifters, and multiply-and-adders has been achieved by using the unified design. These area-effective techniques are useful for embedded microprocessors and scalable systems that employ highly parallel superscalar and on-chip parallel architectures. The integer-media unit has been implemented in an evaluation chip fabricated with 0.15-μm 5-metal CMOS technology.

Original languageEnglish
Pages (from-to)1014-1020
Number of pages7
JournalIEICE Transactions on Electronics
VolumeE84-C
Issue number8
Publication statusPublished - 2001 Aug
Externally publishedYes

Keywords

  • Area-efficiency
  • Embedded microprocessor
  • Multiplier
  • Onchip multiprocessor
  • SIMD

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • Cite this

    Inoue, T., Manabe, T., Torii, S., Masushita, S., Edahiro, M., Nishi, N., & Yamashina, M. (2001). An area-effective datapath architecture for embedded microprocessors and scalable systems. IEICE Transactions on Electronics, E84-C(8), 1014-1020.