TY - GEN
T1 - An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder
AU - Sun, Heming
AU - Zhou, Dajiang
AU - Zhu, Jiayi
AU - Kimura, Shinji
AU - Goto, Satoshi
PY - 2015/2/27
Y1 - 2015/2/27
N2 - This paper presents a new VLSI architecture for HEVC inverse discrete cosine transform (TDCT). Compared to prior arts, this work reduces hardware cost by 1) reducing computational logic of 1-D IDCTs with a reordered parallel-in serial-out (RPISO) scheme that shares the inputs of the butterfly structure, and 2) reducing the area of the transpose buffer with a cyclic memory organization that achieves 100% I/O utilization of the SRAMs. In the implementation of a unified 4/8/16/32-point IDCT, the proposed schemes demonstrate 35% and 62% reduction of logic and memory costs, respectively. The IDCT implementation can support real-time decoding of 4K×2K 60fps video with a total hardware cost of 357,250um2 on 2-D IDCT and 80,988um2 on transpose memory in 90nm process.
AB - This paper presents a new VLSI architecture for HEVC inverse discrete cosine transform (TDCT). Compared to prior arts, this work reduces hardware cost by 1) reducing computational logic of 1-D IDCTs with a reordered parallel-in serial-out (RPISO) scheme that shares the inputs of the butterfly structure, and 2) reducing the area of the transpose buffer with a cyclic memory organization that achieves 100% I/O utilization of the SRAMs. In the implementation of a unified 4/8/16/32-point IDCT, the proposed schemes demonstrate 35% and 62% reduction of logic and memory costs, respectively. The IDCT implementation can support real-time decoding of 4K×2K 60fps video with a total hardware cost of 357,250um2 on 2-D IDCT and 80,988um2 on transpose memory in 90nm process.
KW - HEVC
KW - IDCT
KW - SRAM
KW - area-efficient
KW - video coding
UR - http://www.scopus.com/inward/record.url?scp=84925447183&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84925447183&partnerID=8YFLogxK
U2 - 10.1109/VCIP.2014.7051538
DO - 10.1109/VCIP.2014.7051538
M3 - Conference contribution
AN - SCOPUS:84925447183
T3 - 2014 IEEE Visual Communications and Image Processing Conference, VCIP 2014
SP - 197
EP - 200
BT - 2014 IEEE Visual Communications and Image Processing Conference, VCIP 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2014 IEEE Visual Communications and Image Processing Conference, VCIP 2014
Y2 - 7 December 2014 through 10 December 2014
ER -