An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder

Heming Sun, Dajiang Zhou, Jiayi Zhu, Shinji Kimura, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

This paper presents a new VLSI architecture for HEVC inverse discrete cosine transform (TDCT). Compared to prior arts, this work reduces hardware cost by 1) reducing computational logic of 1-D IDCTs with a reordered parallel-in serial-out (RPISO) scheme that shares the inputs of the butterfly structure, and 2) reducing the area of the transpose buffer with a cyclic memory organization that achieves 100% I/O utilization of the SRAMs. In the implementation of a unified 4/8/16/32-point IDCT, the proposed schemes demonstrate 35% and 62% reduction of logic and memory costs, respectively. The IDCT implementation can support real-time decoding of 4K×2K 60fps video with a total hardware cost of 357,250um2 on 2-D IDCT and 80,988um2 on transpose memory in 90nm process.

Original languageEnglish
Title of host publication2014 IEEE Visual Communications and Image Processing Conference, VCIP 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages197-200
Number of pages4
ISBN (Electronic)9781479961399
DOIs
Publication statusPublished - 2015 Feb 27
Event2014 IEEE Visual Communications and Image Processing Conference, VCIP 2014 - Valletta, Malta
Duration: 2014 Dec 72014 Dec 10

Publication series

Name2014 IEEE Visual Communications and Image Processing Conference, VCIP 2014

Other

Other2014 IEEE Visual Communications and Image Processing Conference, VCIP 2014
CountryMalta
CityValletta
Period14/12/714/12/10

Keywords

  • HEVC
  • IDCT
  • SRAM
  • area-efficient
  • video coding

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Computer Vision and Pattern Recognition

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