An area/time optimizing algorithm in high-level synthesis for control-based hardwares

Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

This paper proposes an area/time optimizing algorithm in high-level synthesis for control-based hardwares. Given a call graph whose node corresponds to a control flow of an application program, the algorithm generates a set of state-transition graphs which represents the input call graph under area and timing constraint. In the algorithm, first state-transition graphs which satisfy only timing constraint are generated and second they are transformed so that they can satisfy area constraint. Since the algorithm is directly applied to control-flow graphs, it can deal with control flows such as bit-wise processes and conditional branches. Further, the algorithm synthesizes more than one hardware architecture candidates from a single call graph for an application program. Designers of an application program can select several good hardware architectures among candidates depending on multiple design criteria. Experimental results for several control-based hardwares demonstrate effectiveness and efficiency of the algorithm.

Original languageEnglish
Title of host publicationProceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
Pages309-312
Number of pages4
DOIs
Publication statusPublished - 2000 Dec 1
Event2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000 - Yokohama, Japan
Duration: 2000 Jan 252000 Jan 28

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000
CountryJapan
CityYokohama
Period00/1/2500/1/28

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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  • Cite this

    Togawa, N., Ienaga, M., Yanagisawa, M., & Ohtsuki, T. (2000). An area/time optimizing algorithm in high-level synthesis for control-based hardwares. In Proceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000 (pp. 309-312). (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1145/368434.368652