An area/time optimizing algorithm in high-level synthesis of control-based hardwares

Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohsuki

    Research output: Contribution to journalArticle

    1 Citation (Scopus)

    Abstract

    This paper proposes an area/time optimizing algorithm in a high-level synthesis system for control-based hardwares. Given a call graph whose node corresponds to a control flow of an application program, the algorithm generates a set of state-transition graphs which represents the input call graph under area and timing constraint. In the algorithm, first state-transition graphs which satisfy only timing constraint are generated and second they are transformed so that they can satisfy area constraint. Since the algorithm is directly applied to control-flow graphs, it can deal with control flows such as bitwise processes and conditional branches. Further, the algorithm synthesizes more than one hardware architecture candidates from a single call graph for an application program. Designers of an application program can select several good hardware architectures among candidates depending on multiple design criteria. Experimental results for several control-based hardwares demonstrate effectiveness and efficiency of the algorithm.

    Original languageEnglish
    Pages (from-to)1166-1176
    Number of pages11
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE84-A
    Issue number5
    Publication statusPublished - 2001 May

    Fingerprint

    High-level Synthesis
    Hardware
    Application programs
    Graph in graph theory
    Hardware Architecture
    State Transition
    Flow Control
    Flow control
    Timing
    Flow graphs
    Flow Graphs
    Computer hardware
    High level synthesis
    Branch
    Experimental Results
    Vertex of a graph
    Demonstrate

    Keywords

    • Area/time optimization
    • Control-based hardware
    • High-level synthesis
    • Resource allocation
    • Scheduling

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems

    Cite this

    An area/time optimizing algorithm in high-level synthesis of control-based hardwares. / Togawa, Nozomu; Ienaga, Masayuki; Yanagisawa, Masao; Ohsuki, Tatsuo.

    In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E84-A, No. 5, 05.2001, p. 1166-1176.

    Research output: Contribution to journalArticle

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