Abstract
Nowdays, Low-power design, especially Multi-voltage design becomes a popular and efficient way to reduce both dynamic power and static power. In this paper, we propose an efficient method of level-shifter floorplanning for a given multi-voltage design. This method is a two stage optimization method. First, for a given voltage island and its sequence pair representation, we greedily pre-place level-shifters into white-spaces of multi-voltage island based sequence-pair representation. Then, we employ a modified IARFP [1] algorithm to re-optimize the positions of level-shifters. Experimental results show that, the proposed two stage level-shifter floorplanner is efficient for post multi-voltage island optimization.
Original language | English |
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Title of host publication | Proceedings of International Conference on ASIC |
Pages | 421-424 |
Number of pages | 4 |
DOIs | |
Publication status | Published - 2011 |
Event | 2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen Duration: 2011 Oct 25 → 2011 Oct 28 |
Other
Other | 2011 IEEE 9th International Conference on ASIC, ASICON 2011 |
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City | Xiamen |
Period | 11/10/25 → 11/10/28 |
Keywords
- Level-Shifter
- Multi-voltage design
- Voltage-Island
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering