Abstract
With the scaling of CMOS technology into the nanometer regime, the overshooting effect is more and more obvious and has a significant influence to gate delay and power consumption. Recently, researchers have already proposed the overshooting effect models for an inverter. However, the accurate overshooting effect model for multiple-input gates is seldom presented and the existing technology to reduce a multipleinput gate to an inverter is not useful when modeling the overshooting effect for multiple-input gates. Therefore, modeling the overshooting effect for multiple-input gates is proposed in this paper. Firstly, a formula-based model is presented for the overshooting time of 2-input NOR gate. Then, more complicated methods are given to calculate the overshooting time of 3-input NOR gate and other multiple-input gates. The proposed model is verified to have a good agreement, within 3.4% error margin, compared with SPICE simulation results using CMOS 32 nm PTM model.
| Original language | English |
|---|---|
| Pages (from-to) | 1059-1074 |
| Number of pages | 16 |
| Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| Volume | E97-A |
| Issue number | 5 |
| DOIs | |
| Publication status | Published - 2014 |
Fingerprint
Keywords
- Gate delay
- Multiple-input gates
- Nanometer technology
- Overshooting effect
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Computer Graphics and Computer-Aided Design
- Applied Mathematics
- Signal Processing
Cite this
An effective model of the overshooting effect for multiple-input gates in nanometer technologies. / Ding, Li; Huang, Zhangcai; Kurokawa, Atsushi; Wang, Jing; Inoue, Yasuaki.
In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E97-A, No. 5, 2014, p. 1059-1074.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - An effective model of the overshooting effect for multiple-input gates in nanometer technologies
AU - Ding, Li
AU - Huang, Zhangcai
AU - Kurokawa, Atsushi
AU - Wang, Jing
AU - Inoue, Yasuaki
PY - 2014
Y1 - 2014
N2 - With the scaling of CMOS technology into the nanometer regime, the overshooting effect is more and more obvious and has a significant influence to gate delay and power consumption. Recently, researchers have already proposed the overshooting effect models for an inverter. However, the accurate overshooting effect model for multiple-input gates is seldom presented and the existing technology to reduce a multipleinput gate to an inverter is not useful when modeling the overshooting effect for multiple-input gates. Therefore, modeling the overshooting effect for multiple-input gates is proposed in this paper. Firstly, a formula-based model is presented for the overshooting time of 2-input NOR gate. Then, more complicated methods are given to calculate the overshooting time of 3-input NOR gate and other multiple-input gates. The proposed model is verified to have a good agreement, within 3.4% error margin, compared with SPICE simulation results using CMOS 32 nm PTM model.
AB - With the scaling of CMOS technology into the nanometer regime, the overshooting effect is more and more obvious and has a significant influence to gate delay and power consumption. Recently, researchers have already proposed the overshooting effect models for an inverter. However, the accurate overshooting effect model for multiple-input gates is seldom presented and the existing technology to reduce a multipleinput gate to an inverter is not useful when modeling the overshooting effect for multiple-input gates. Therefore, modeling the overshooting effect for multiple-input gates is proposed in this paper. Firstly, a formula-based model is presented for the overshooting time of 2-input NOR gate. Then, more complicated methods are given to calculate the overshooting time of 3-input NOR gate and other multiple-input gates. The proposed model is verified to have a good agreement, within 3.4% error margin, compared with SPICE simulation results using CMOS 32 nm PTM model.
KW - Gate delay
KW - Multiple-input gates
KW - Nanometer technology
KW - Overshooting effect
UR - http://www.scopus.com/inward/record.url?scp=84899744327&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84899744327&partnerID=8YFLogxK
U2 - 10.1587/transfun.E97.A.1059
DO - 10.1587/transfun.E97.A.1059
M3 - Article
AN - SCOPUS:84899744327
VL - E97-A
SP - 1059
EP - 1074
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
SN - 0916-8508
IS - 5
ER -