An effective model of the overshooting effect for multiple-input gates in nanometer technologies

Li Ding, Zhangcai Huang, Atsushi Kurokawa, Jing Wang, Yasuaki Inoue

    Research output: Contribution to journalArticle

    Abstract

    With the scaling of CMOS technology into the nanometer regime, the overshooting effect is more and more obvious and has a significant influence to gate delay and power consumption. Recently, researchers have already proposed the overshooting effect models for an inverter. However, the accurate overshooting effect model for multiple-input gates is seldom presented and the existing technology to reduce a multipleinput gate to an inverter is not useful when modeling the overshooting effect for multiple-input gates. Therefore, modeling the overshooting effect for multiple-input gates is proposed in this paper. Firstly, a formula-based model is presented for the overshooting time of 2-input NOR gate. Then, more complicated methods are given to calculate the overshooting time of 3-input NOR gate and other multiple-input gates. The proposed model is verified to have a good agreement, within 3.4% error margin, compared with SPICE simulation results using CMOS 32 nm PTM model.

    Original languageEnglish
    Pages (from-to)1059-1074
    Number of pages16
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE97-A
    Issue number5
    DOIs
    Publication statusPublished - 2014

    Keywords

    • Gate delay
    • Multiple-input gates
    • Nanometer technology
    • Overshooting effect

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Graphics and Computer-Aided Design
    • Applied Mathematics
    • Signal Processing

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