An effective suspicious timing-error prediction circuit insertion algorithm minimizing area overhead

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

As process technologies advance, timing-error correction techniques have become important as well. A suspicious timing-error prediction (STEP) technique has been proposed recently, which predicts timing errors by monitoring themiddle points, or check points of several speedpaths in a circuit. However, if we insert STEP circuits (STEPCs) in the middle points of all the paths from primary inputs to primary outputs, we need many STEPCs and thus require too much area overhead. How to determine these check points is very important. In this paper, we propose an effective STEPC insertion algorithm minimizing area overhead. Our proposed algorithm moves the STEPC insertion positions to minimize inserted STEPC counts. We apply a max-flow and min-cut approach to determine the optimal positions of inserted STEPCs and reduce the required number of STEPCs to 1/10-1/80 and their area to 1/5-1/8 compared with a naive algorithm. Furthermore, our algorithm realizes 1.12X-1.5X overclocking compared with just inserting STEPCs into several speed-paths.

Original languageEnglish
Pages (from-to)1406-1418
Number of pages13
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE98A
Issue number7
DOIs
Publication statusPublished - 2015 Jul 1

Keywords

  • Delay variation
  • Overclocking
  • Robust design
  • Timing-error prediction

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

Fingerprint Dive into the research topics of 'An effective suspicious timing-error prediction circuit insertion algorithm minimizing area overhead'. Together they form a unique fingerprint.

Cite this