Abstract
As process technologies advance, timing-error correction techniques have become important as well. A suspicious timing-error prediction (STEP) technique has been proposed recently, which predicts timing errors by monitoring themiddle points, or check points of several speedpaths in a circuit. However, if we insert STEP circuits (STEPCs) in the middle points of all the paths from primary inputs to primary outputs, we need many STEPCs and thus require too much area overhead. How to determine these check points is very important. In this paper, we propose an effective STEPC insertion algorithm minimizing area overhead. Our proposed algorithm moves the STEPC insertion positions to minimize inserted STEPC counts. We apply a max-flow and min-cut approach to determine the optimal positions of inserted STEPCs and reduce the required number of STEPCs to 1/10-1/80 and their area to 1/5-1/8 compared with a naive algorithm. Furthermore, our algorithm realizes 1.12X-1.5X overclocking compared with just inserting STEPCs into several speed-paths.
| Original language | English |
|---|---|
| Pages (from-to) | 1406-1418 |
| Number of pages | 13 |
| Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| Volume | E98A |
| Issue number | 7 |
| DOIs | |
| Publication status | Published - 2015 Jul 1 |
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Keywords
- Delay variation
- Overclocking
- Robust design
- Timing-error prediction
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Computer Graphics and Computer-Aided Design
- Applied Mathematics
- Signal Processing
Cite this
An effective suspicious timing-error prediction circuit insertion algorithm minimizing area overhead. / Yoshida, Shinnosuke; Shi, Youhua; Yanagisawa, Masao; Togawa, Nozomu.
In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E98A, No. 7, 01.07.2015, p. 1406-1418.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - An effective suspicious timing-error prediction circuit insertion algorithm minimizing area overhead
AU - Yoshida, Shinnosuke
AU - Shi, Youhua
AU - Yanagisawa, Masao
AU - Togawa, Nozomu
PY - 2015/7/1
Y1 - 2015/7/1
N2 - As process technologies advance, timing-error correction techniques have become important as well. A suspicious timing-error prediction (STEP) technique has been proposed recently, which predicts timing errors by monitoring themiddle points, or check points of several speedpaths in a circuit. However, if we insert STEP circuits (STEPCs) in the middle points of all the paths from primary inputs to primary outputs, we need many STEPCs and thus require too much area overhead. How to determine these check points is very important. In this paper, we propose an effective STEPC insertion algorithm minimizing area overhead. Our proposed algorithm moves the STEPC insertion positions to minimize inserted STEPC counts. We apply a max-flow and min-cut approach to determine the optimal positions of inserted STEPCs and reduce the required number of STEPCs to 1/10-1/80 and their area to 1/5-1/8 compared with a naive algorithm. Furthermore, our algorithm realizes 1.12X-1.5X overclocking compared with just inserting STEPCs into several speed-paths.
AB - As process technologies advance, timing-error correction techniques have become important as well. A suspicious timing-error prediction (STEP) technique has been proposed recently, which predicts timing errors by monitoring themiddle points, or check points of several speedpaths in a circuit. However, if we insert STEP circuits (STEPCs) in the middle points of all the paths from primary inputs to primary outputs, we need many STEPCs and thus require too much area overhead. How to determine these check points is very important. In this paper, we propose an effective STEPC insertion algorithm minimizing area overhead. Our proposed algorithm moves the STEPC insertion positions to minimize inserted STEPC counts. We apply a max-flow and min-cut approach to determine the optimal positions of inserted STEPCs and reduce the required number of STEPCs to 1/10-1/80 and their area to 1/5-1/8 compared with a naive algorithm. Furthermore, our algorithm realizes 1.12X-1.5X overclocking compared with just inserting STEPCs into several speed-paths.
KW - Delay variation
KW - Overclocking
KW - Robust design
KW - Timing-error prediction
UR - http://www.scopus.com/inward/record.url?scp=84937622478&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84937622478&partnerID=8YFLogxK
U2 - 10.1587/transfun.E98.A.1406
DO - 10.1587/transfun.E98.A.1406
M3 - Article
AN - SCOPUS:84937622478
VL - E98A
SP - 1406
EP - 1418
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
SN - 0916-8508
IS - 7
ER -