An efficient deadlock-free adaptive routing algorithm for 3D network-on-chips

Jindun Dai, Xin Jiang, Renjie Li, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Network-on-Chips (NoC) has been proven as a flexible solution for Chip-Multiprocessor (CMP) systems due to its reusability and scalability. To increase communication efficiency, Three-Dimensional Networks-on-Chips (3D NoCs) are developed, which can shorten the wire length and improve the system performance. In this paper, we present a novel deadlock-free adaptive routing algorithm for 3D mesh NoC interconnections. The routing rules of traditional XY routing and YX routing are relaxed and used for intra-layer routing. Via multiple layers, balanced adaptiveness can be achieved. We detail the basic principle of this method and test its efficiency through simulations.

Original languageEnglish
Title of host publicationProceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages29-36
Number of pages8
Volume2018-January
ISBN (Electronic)9781538634417
DOIs
Publication statusPublished - 2018 Mar 26
Event11th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017 - Seoul, Korea, Republic of
Duration: 2017 Sep 182017 Sep 20

Other

Other11th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017
CountryKorea, Republic of
CitySeoul
Period17/9/1817/9/20

Fingerprint

Routing algorithms
Adaptive algorithms
Reusability
Scalability
Wire
Communication
Network-on-chip

Keywords

  • 3D network-on-chip
  • adaptive routing
  • computer architecture
  • multiprocessing systems

ASJC Scopus subject areas

  • Safety, Risk, Reliability and Quality
  • Hardware and Architecture
  • Signal Processing

Cite this

Dai, J., Jiang, X., Li, R., & Watanabe, T. (2018). An efficient deadlock-free adaptive routing algorithm for 3D network-on-chips. In Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017 (Vol. 2018-January, pp. 29-36). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MCSoC.2017.10

An efficient deadlock-free adaptive routing algorithm for 3D network-on-chips. / Dai, Jindun; Jiang, Xin; Li, Renjie; Watanabe, Takahiro.

Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. p. 29-36.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dai, J, Jiang, X, Li, R & Watanabe, T 2018, An efficient deadlock-free adaptive routing algorithm for 3D network-on-chips. in Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017. vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 29-36, 11th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017, Seoul, Korea, Republic of, 17/9/18. https://doi.org/10.1109/MCSoC.2017.10
Dai J, Jiang X, Li R, Watanabe T. An efficient deadlock-free adaptive routing algorithm for 3D network-on-chips. In Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017. Vol. 2018-January. Institute of Electrical and Electronics Engineers Inc. 2018. p. 29-36 https://doi.org/10.1109/MCSoC.2017.10
Dai, Jindun ; Jiang, Xin ; Li, Renjie ; Watanabe, Takahiro. / An efficient deadlock-free adaptive routing algorithm for 3D network-on-chips. Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. pp. 29-36
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